Senior Design Verification Engineer (DDR6 & Memory)

Renesas Electronics Corp.; Duluth (GA); On-site; USD 120,000 - 180,000; Full time

Benefits offered by this job

Medical insurance

HSAs and other benefits

Dental insurance

Vision insurance

Life insurance

Job summary

Renesas Electronics Corp. seeks an experienced Staff Design Verification Engineer to join our team focused on memory interface products for data center, AI, and cloud computing applications.

You will verify DDR6 memory interfaces and future generations, employing SystemVerilog and UVM in advanced verification environments. The role emphasizes ownership of verification for blocks and features, development of tests and coverage, and collaboration with design engineers to ensure verifiability and

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
• 8+ years of related experience in semiconductor design verification.
• Strong experience in semiconductor design verification.
• Strong proficiency with SystemVerilog and hands-on experience using UVM (Universal Verification Methodology).
• Experience developing and debugging UVM-based verification environments and testbenches.

Responsibilities

• Drive verification activities for complex digital designs at the block and system level.
• Develop and execute verification plans based on functional and performance specifications.
• Develop, maintain, and optimize SystemVerilog/UVM verification environments and testbenches.
• Develop verification tests, functional coverage, checkers, and other verification components.
• Take ownership of verification environments and verification execution for assigned blocks and features.
• Drive and monitor coverage to ensure verification goals are achieved.
• Work closely with design engineers to ensure designs meet requirements and are effectively verifiable.
• Analyze verification results, debug failures, and identify functional or design issues.
• Develop efficient, reusable verification environments and methodologies with a focus on quality, performance, and ease of use.
• Identify and implement improvements to verification processes, methodologies, and design behavior.
• Participate in feasibility studies and technical reviews.
• Serve as a technical resource within the team, providing guidance on complex verification problems and sharing best practices.
• Communicate verification status, risks, and results to project stakeholders.

Skills

SystemVerilog

UVM

Analytical skills

Problem-solving

Education

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Tools

UVM-based testbenches

Job description

Renesas Electronics Corp. seeks an experienced Staff Design Verification Engineer to join our team focused on memory interface products for data center, AI, and cloud computing applications.

You will verify DDR6 memory interfaces and future generations, employing SystemVerilog and UVM in advanced verification environments. The role emphasizes ownership of verification for blocks and features, development of tests and coverage, and collaboration with design engineers to ensure verifiability and