Staff Design Verification Engineer DDR6 & SystemVerilog/UVM

Renesas; Melbourne (FL); On-site; USD 140,000 - 170,000; Full time

Benefits offered by this job

Medical benefits

Health savings account (HSA)

Dental

Vision

Commuter benefits

Life insurance

AD&D

Pet insurance

Job summary

Renesas is seeking an experienced Staff Design Verification Engineer to join our team developing memory interface products for data center, AI, and cloud computing applications. The role focuses on verifying DDR6 generations with SystemVerilog and UVM.

Ideal candidates have 8+ years in semiconductor verification, strong SystemVerilog/UVM skills, and the ability to own complex verification tasks while collaborating with design teams. Willingness to relocate to Duluth, GA is required.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
• 8+ years of experience in semiconductor design verification.
• Strong proficiency with SystemVerilog and hands-on experience using UVM.
• Experience developing and debugging UVM-based verification environments and testbenches.

Responsibilities

• Drive verification activities for complex digital designs at the block and system level.
• Develop and execute verification plans based on functional and performance specifications.
• Develop, maintain, and optimize SystemVerilog/UVM verification environments and testbenches.
• Develop verification tests, functional coverage, checkers, and other verification components.
• Take ownership of verification environments and verification execution for assigned blocks and features.
• Drive and monitor coverage to ensure verification goals are achieved.
• Work closely with design engineers to ensure designs meet requirements and are verifiable.
• Analyze verification results, debug failures, and identify issues.
• Develop efficient, reusable verification environments and methodologies with focus on quality and performance.

Skills

SystemVerilog

UVM

Memory verification

Verification planning

Debugging

DDR memory

Collaboration

Education

Bachelor's or Master's in Electrical/Computer Engineering or related field

Job description

Renesas is seeking an experienced Staff Design Verification Engineer to join our team developing memory interface products for data center, AI, and cloud computing applications. The role focuses on verifying DDR6 generations with SystemVerilog and UVM.

Ideal candidates have 8+ years in semiconductor verification, strong SystemVerilog/UVM skills, and the ability to own complex verification tasks while collaborating with design teams. Willingness to relocate to Duluth, GA is required.