Staff Design Verification Engineer — DDR6 & UVM Expert

Renesas Electronics; Raleigh (NC); On-site; USD 120,000 - 180,000; Full time

Benefits offered by this job

Medical benefits

401(k) matching

Paid time off

Job summary

Renesas Electronics seeks an experienced Staff Design Verification Engineer to advance memory interface products for data centers, AI, and cloud computing. The role emphasizes SystemVerilog/UVM verification of high‑speed memory buffers, with a focus on block and system level design validation and robust testbench development.

The ideal candidate has 8+ years in semiconductor verification, strong SystemVerilog/UVM skills, and DDR memory experience.

Qualifications

• 8+ years of semiconductor design verification experience.
• Strong proficiency with SystemVerilog and hands-on UVM.
• Experience with DDR memory interfaces and verification planning is a plus.

Responsibilities

• Drive verification activities for complex digital designs at block and system levels.
• Develop and execute verification plans based on functional and performance specs.
• Develop, maintain, and optimize SystemVerilog/UVM environments and testbenches.
• Create verification tests, functional coverage, checkers, and other verification components.
• Own verification environments and execution for assigned blocks and features.
• Monitor coverage and ensure verification goals are met.

Skills

SystemVerilog

UVM

DDR memory

Verification

Education

Bachelor’s or Master’s in Electrical/Computer Engineering or CS

Job description

Renesas Electronics seeks an experienced Staff Design Verification Engineer to advance memory interface products for data centers, AI, and cloud computing. The role emphasizes SystemVerilog/UVM verification of high‑speed memory buffers, with a focus on block and system level design validation and robust testbench development.

The ideal candidate has 8+ years in semiconductor verification, strong SystemVerilog/UVM skills, and DDR memory experience.