Senior Memory Verification Architect (DDR6)

Renesas Electronics; Tampa (FL); On-site; USD 150,000 - 190,000; Full time

Benefits offered by this job

Medical benefits

Life Insurance

401(k) retirement plan

Job summary

Renesas Electronics is seeking a Senior Staff Design Verification Engineer to provide technical leadership for the verification of memory interface products used in data center, AI, and cloud workloads. Expertise in SystemVerilog/UVM and memory data buffers will help guide verification strategy for DDR6 and beyond.

The role emphasizes leading verification environments, testplans, and coverage, while mentoring engineers and coordinating across teams to reach milestones.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• 10+ years of semiconductor design verification experience.
• Deep experience in semiconductor design verification with technical leadership.
• Advanced proficiency with SystemVerilog and extensive hands-on experience with UVM.
• Experience defining verification strategies and developing verification plans from specs.
• Strong experience in constructing UVM-based environments and testbenches.
• Ability to mentor engineers and guide verification methodology decisions.

Responsibilities

• Provide technical leadership for verification of complex semiconductor designs at block and system level.
• Define and drive verification strategies, test plans, and coverage approaches.
• Lead development and optimization of SystemVerilog/UVM verification environments and testbenches.
• Drive functional verification, coverage, debugging, and coverage closure.
• Mentor verification engineers and coordinate with design teams to meet milestones.
• Communicate verification status and risk to engineering leadership.

Skills

SystemVerilog

UVM

Verification leadership

Testbench development

Debugging

Memory interfaces

Education

Bachelor's or Master's in Electrical Engineering or Computer Engineering or CS

Tools

SystemVerilog

UVM

Job description

Renesas Electronics is seeking a Senior Staff Design Verification Engineer to provide technical leadership for the verification of memory interface products used in data center, AI, and cloud workloads. Expertise in SystemVerilog/UVM and memory data buffers will help guide verification strategy for DDR6 and beyond.

The role emphasizes leading verification environments, testplans, and coverage, while mentoring engineers and coordinating across teams to reach milestones.