Senior Memory Verification Architect (DDR6, SV/UVM)

SmartRecruiters, Inc.; Duluth (GA); On-site; USD 150,000 - 190,000; Full time

Benefits offered by this job

Health insurance

Dental & Vision

401(k) plan

Life insurance

Paid time off

Job summary

Renesas Electronics is seeking a Senior Staff Design Verification Engineer to provide technical leadership for verification of memory interface products used in data center, AI, and cloud applications. The role focuses on DDR6 and future generations, with expert use of SystemVerilog and UVM.

The ideal candidate has 10+ years in semiconductor verification, can drive verification strategies, and mentor engineers.

Qualifications

• 10+ years of semiconductor design verification experience.
• Strong SystemVerilog and UVM expertise.
• Ability to lead verification strategies and teams.
• Experience with DDR4/DDR5 memory interfaces is a plus.

Responsibilities

• Provide technical leadership for verification of complex semiconductor designs at the block and system level.
• Define and drive verification strategies, methodologies, test plans, and coverage approaches for complex designs and features.
• Lead the development and optimization of SystemVerilog/UVM verification environments and testbenches.
• Drive verification execution, functional coverage, debugging, and coverage closure.
• Take ownership of significant verification efforts and make independent technical decisions regarding verification methods, techniques, and priorities.
• Work closely with design engineers and other technical stakeholders to ensure designs meet functional and performance requirements and are verifiably correct.
• Analyze complex verification and design issues, determine root causes, and drive solutions.
• Anticipate technical challenges and identify improvements to verification methodologies, processes, quality, and efficiency.
• Drive the development of reusable verification solutions, methodologies, and best practices that can benefit broader engineering efforts.
• Participate in architecture, feasibility, design, and technical reviews and provide leadership during sessions.
• Serve as a subject matter expert in design verification and provide technical guidance on complex problems.
• Mentor and provide guidance to verification engineers across projects and experience levels.
• Coordinate with stakeholders across teams to achieve milestones and objectives.
• Communicate verification status, risks, and readiness to engineering leadership and stakeholders.

Skills

SystemVerilog

UVM

Verification leadership

DDR memory interface

Mentoring engineers

Education

Bachelor's or Master's in Electrical/Computer Engineering or Computer Science

Tools

SystemVerilog

UVM

Job description

Renesas Electronics is seeking a Senior Staff Design Verification Engineer to provide technical leadership for verification of memory interface products used in data center, AI, and cloud applications. The role focuses on DDR6 and future generations, with expert use of SystemVerilog and UVM.

The ideal candidate has 10+ years in semiconductor verification, can drive verification strategies, and mentor engineers.