Staff Design Verification Architect - DDR6/UVM

Renesas Electronics Corporation; Duluth (GA); On-site; USD 120,000 - 190,000; Full time

Benefits offered by this job

Medical benefits

Dental & Vision insurance

Paid time off

Job summary

Renesas Electronics Corporation invites an experienced Staff Design Verification Engineer to join our memory interface team. You will verify DDR6 and future generations, develop UVM-based verification environments, and drive coverage and quality for high-speed memory blocks.

Ideal candidates have 8+ years in semiconductor design verification, SystemVerilog expertise, and strong problem-solving skills. This role collaborates with design and software teams to deliver robust, verifiable memory

Qualifications

• 8+ years of semiconductor design verification experience.
• Strong proficiency with SystemVerilog and hands-on experience using UVM.
• Experience with verification planning, functional verification, coverage, checkers, test development, and debugging.

Responsibilities

• Drive verification activities for complex digital designs at the block and system level.
• Develop and execute verification plans based on functional and performance specifications.
• Develop, maintain, and optimize SystemVerilog/UVM verification environments and testbenches.
• Develop verification tests, functional coverage, checkers, and other verification components.
• Take ownership of verification environments and verification execution for assigned blocks and features.
• Drive and monitor coverage to ensure verification goals are achieved.
• Work closely with design engineers to ensure designs meet requirements and are effectively verifiable.
• Analyze verification results, debug failures, and identify functional or design issues.

Skills

SystemVerilog

UVM

Memory interface design

Education

Bachelor's or Master's in Electrical / Computer Engineering / Computer Science

Tools

UVM (Universal Verification Methodology)

Job description

Renesas Electronics Corporation invites an experienced Staff Design Verification Engineer to join our memory interface team. You will verify DDR6 and future generations, develop UVM-based verification environments, and drive coverage and quality for high-speed memory blocks.

Ideal candidates have 8+ years in semiconductor design verification, SystemVerilog expertise, and strong problem-solving skills. This role collaborates with design and software teams to deliver robust, verifiable memory