Staff Design Verification Engineer - DDR6 & Memory

Renesas; Tampa (FL); On-site; USD 140,000 - 185,000; Full time

Job summary

Renesas seeks a Staff Design Verification Engineer to lead verification for advanced memory interface products (DDR6 and beyond) in a fast-paced data center, AI and cloud computing environment. The role requires SystemVerilog/UVM expertise and 8+ years in semiconductor verification, with relocation to the Duluth, GA area.

Responsibilities include driving block/system level verification, developing verification plans, and owning testbenches and coverage.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field, or equivalent experience.
• 8+ years of related experience in semiconductor design verification.
• Strong proficiency with SystemVerilog and hands-on experience using UVM (Universal Verification Methodology).
• Experience developing and debugging UVM-based verification environments and testbenches.
• Experience with verification planning, functional verification, coverage, checkers, test development, and debugging.
• Ability to independently own complex verification assignments and determine appropriate verification approaches.
• Strong analytical and problem-solving skills.

Responsibilities

• Drive verification activities for complex digital designs at the block and system level.
• Develop and execute verification plans based on functional and performance specifications.
• Develop, maintain, and optimize SystemVerilog/UVM verification environments and testbenches.
• Develop verification tests, functional coverage, checkers, and other verification components.
• Take ownership of verification environments and verification execution for assigned blocks and features.
• Drive and monitor coverage to ensure verification goals are achieved.
• Work closely with design engineers to ensure designs meet requirements and are effectively verifiable.
• Analyze verification results, debug failures, and identify functional or design issues.
• Develop efficient, reusable verification environments and methodologies with a focus on quality, performance, and ease of use.
• Identify and implement improvements to verification processes, methodologies, and design behavior.
• Participate in feasibility studies and technical reviews.
• Serve as a technical resource within the team, providing guidance on complex verification problems and sharing best practices.
• Communicate verification status, risks, and results to project stakeholders.

Skills

SystemVerilog

UVM

Memory verification

Analytical thinking

Problem solving

Education

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field

Job description

Renesas seeks a Staff Design Verification Engineer to lead verification for advanced memory interface products (DDR6 and beyond) in a fast-paced data center, AI and cloud computing environment. The role requires SystemVerilog/UVM expertise and 8+ years in semiconductor verification, with relocation to the Duluth, GA area.

Responsibilities include driving block/system level verification, developing verification plans, and owning testbenches and coverage.