Senior SRAM Layout Engineer - Custom Memory IP

Trinus Corporation; Santa Clara (CA); On-site; USD 180,000 - 260,000; Full time

Job summary

Trinus Corporation in Santa Clara, California seeks an experienced IC layout engineer to manage complete custom layout for SRAM and memory IP in advanced CMOS nodes. You will drive layout planning, ensure symmetry and reliability, and collaborate closely with circuit designers and PnR teams.

Join a team focused on high-quality memory IP delivery, mentoring engineers, advancing layout methodology, and ensuring successful tape-out with cutting-edge process nodes.

Qualifications

• BSEE or equivalent required.
• 10+ years in custom IC layout.
• 5+ years SRAM/memory IP layout.
• Experience with CMOS FinFET/GAA nodes.
• Proficiency with Cadence Virtuoso.
• Strong debugging with Calibre/ICV.

Responsibilities

• Develop and improve SRAM and memory layouts.
• Mentor junior engineers and review layouts.
• Collaborate with PnR, CAD, and foundry teams.
• Perform DRC/LVS/ER checks and optimize density.
• Lead layout validation for tape-out readiness.

Skills

IC layout

SRAM memory

Cadence Virtuoso

DRC/LVS debugging

Floor planning

Physical verification

FinFET/GAA

Cross-functional collab

Education

BSEE or equivalent

Tools

Calibre

ICV

Job description

Trinus Corporation in Santa Clara, California seeks an experienced IC layout engineer to manage complete custom layout for SRAM and memory IP in advanced CMOS nodes. You will drive layout planning, ensure symmetry and reliability, and collaborate closely with circuit designers and PnR teams.

Join a team focused on high-quality memory IP delivery, mentoring engineers, advancing layout methodology, and ensuring successful tape-out with cutting-edge process nodes.