Senior IC Layout Engineer – SRAM & Memory IP

MetAntz; Santa Clara (CA); On-site; USD 180,000 - 280,000; Full time

Job summary

MetAntz is seeking a Senior Custom IC Layout Engineer to lead the full custom layout process for SRAM bitcell arrays and memory macros in advanced CMOS technologies. You will develop floorplans, perform physical verifications, and collaborate across CAD, foundry, and circuit teams to ensure high-quality memory IP delivery.

You will mentor engineers, improve layout methodology, and address top-level design challenges with a hands-on, detail-oriented approach in a fast-paced environment.

Qualifications

• BSEE or equivalent required.
• 10+ years of custom IC layout experience including SRAM/memory IP.
• Hands-on with FinFET/GAA at 5nm or smaller.
• Proficiency with Cadence Virtuoso for custom layout.
• Experience with DRC/LVS using Calibre/ICV.
• Ability to mentor engineers.

Responsibilities

• Manage the complete custom layout process for SRAM bitcell arrays, memory periphery, test structures, and memory macros in advanced CMOS technologies.
• Develop and improve floorplans for SRAM and memory blocks, covering array layout, periphery positioning, power grid design, routing channels, and macro assembly.
• Carry out, debug, and complete DRC, LVS, ERC, antenna, and related checks with tools such as Calibre, ICV, or similar workflows.
• Support EM, IR review, power integrity, density, fill, DFM, dummy insertion, layout-dependent effects, and tapeout requirements.
• Collaborate with circuit designers to convert schematics into layouts, ensuring matching, symmetry, shielding, parasitic targets, and reliability constraints.
• Collaborate with PnR and integration teams to resolve top-level DRC, LVS, pin access, boundary, routing, power-grid, and macro-integration issues.
• Implement and advance layout methodology, checklists, reusable practices, and quality standards for consistent memory IP delivery.
• Collaborate with foundry, CAD, and methodology teams on rule interpretation, deck behavior, waivers, and advanced-node process constraints.
• Review layouts, mentor junior engineers, and help raise layout quality and execution rigor across the team.

Skills

SRAM/memory IP layout

Floorplanning

Mentoring

Collaboration with CAD/Foundry

Leadership / ownership

Advanced-node FinFET/5nm

Layout automation / AI tools

Strong communication

Education

BSEE or equivalent

Tools

Cadence Virtuoso

Calibre/ICV

Job description

MetAntz is seeking a Senior Custom IC Layout Engineer to lead the full custom layout process for SRAM bitcell arrays and memory macros in advanced CMOS technologies. You will develop floorplans, perform physical verifications, and collaborate across CAD, foundry, and circuit teams to ensure high-quality memory IP delivery.

You will mentor engineers, improve layout methodology, and address top-level design challenges with a hands-on, detail-oriented approach in a fast-paced environment.