Layout Design Engineer

Infobahn Softworld Inc; Santa Clara (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

NVIDIA's memory IP group seeks a Senior SRAM / Memory Custom Layout Engineer to lead full-custom layout for SRAM bitcells, memory periphery, and macros in advanced CMOS. You will collaborate with circuit design, CAD, and foundry teams to deliver tapeouts in FinFET/GAA nodes.

Requires a BSEE or equivalent, 10+ years in custom IC layout, 5+ years SRAM/memory IP layout, and expert Cadence Virtuoso usage; knowledge of Calibre/ICV for DRC/LVS is essential; contribute to layout methodologies and

Qualifications

• BSEE or equivalent technical experience.
• 10+ years of custom IC layout experience.
• 5+ years SRAM, memory IP layout experience.
• Strong experience with advanced CMOS technologies, FinFET/GAA 5nm/3nm+.
• Deep understanding SRAM and memory layout architectures.
• Extensive hands-on Cadence Virtuoso for custom layout.
• Strong experience debugging DRC/LVS with Calibre/ICV.
• Collaborate with circuit design, CAD, foundry teams.

Responsibilities

• Own the complete custom layout process for SRAM bitcell arrays, memory periphery, test structures, and memory macros.
• Develop and optimize floorplans for SRAM and memory blocks with power grids and routing channels.
• Create and debug custom layouts using Cadence Virtuoso.
• Resolve DRC, LVS, ERC, antenna, and physical verification issues using Calibre/ICV.
• Support EM/IR, power integrity, density/fill, DFM and tapeout requirements.
• Translate schematics into high-quality layouts while ensuring matching, symmetry, shielding.
• Collaborate with PnR/integration teams to address top-level issues.
• Develop layout methodologies, checklists, and reusable practices.

Skills

SRAM layout

Advanced CMOS layouts

Cadence Virtuoso

Floorplanning

DRC/LVS debugging

Mentoring

Education

BSEE or equivalent

Tools

Cadence Virtuoso

Calibre

ICV

Job description

Senior SRAM / Memory Custom Layout Engineer

12+ Months Contract

Client: NVIDIA

Position Overview

We are seeking a highly experienced Senior SRAM / Memory Custom Layout Engineer to lead custom physical layout development for SRAM bitcell arrays, memory periphery, test structures, and memory macros in advanced CMOS technologies. The ideal candidate will have deep expertise in full-custom IC layout, SRAM/memory IP, advanced-node physical verification, and Cadence Virtuoso, with strong hand-on experience at FinFET/GAA nodes such as 5nm, 3nm, or below.

This role will work closely with circuit design, physical implementation, integration, CAD, methodology, and foundry teams to deliver high-quality memory IP through tapeout.

Key Responsibilities

• Own the complete custom layout process for SRAM bitcell arrays, memory periphery, test structures, and memory macros.
• Develop and optimize floorplans for SRAM and memory blocks, including array organization, periphery placement, power grids, routing channels, and macro assembly.
• Create and debug custom layouts using Cadence Virtuoso.
• Execute and resolve DRC, LVS, ERC, antenna, and physical verification issues using Calibre, ICV, or equivalent tools.
• Support EM/IR, power integrity, density/fill, DFM, dummy insertion, and layout-dependent effect requirements for tapeout.
• Translate circuit schematics into high-quality custom layouts while maintaining:
  • Matching
  • Symmetry
  • Shielding
  • Parasitic targets
  • Reliability requirements
• Partner with PnR and integration teams to resolve top-level:
  • DRC/LVS issues
  • Pin-access problems
  • Boundary/interface issues
  • Routing conflicts
  • Power-grid issues
  • Memory macro integration issues
• Develop and improve layout methodologies, checklists, reusable practices, and quality standards.
• Work with foundry, CAD, and methodology teams on process rules, rule-deck behavior, waivers, and advanced-node constraints.
• Review layouts and provide technical guidance and mentorship to junior layout engineers.
• Help improve layout quality, productivity, consistency, and tapeout execution.
• Evaluate and leverage layout automation, scripting, and AI-assisted tools where applicable.

Required Qualifications

• BSEE or equivalent technical experience.
• 10+ years of custom IC layout experience.
• 5+ years of hand-on SRAM, memory compiler, or full-custom memory IP layout experience.
• Strong experience with advanced CMOS technologies, preferably FinFET or GAA at 5nm, 3nm, or smaller nodes.
• Deep understanding of SRAM and memory layout architecture and methodologies.
• Extensive hand-on experience with Cadence Virtuoso for custom layout creation, editing, and verification.
• Strong experience debugging DRC/LVS using Calibre, ICV, or similar physical verification tools.
• Experience with:
  • Floorplanning
  • Block-level routing
  • Pin planning
  • Boundary/interface management
  • Strong understanding of advanced-node physical effects and constraints, including:
    • LOD
    • Matching and symmetry
    • Shielding
    • EM/IR
    • IR drop
    • DFM
  • Ability to collaborate effectively with circuit design, physical implementation, integration, CAD, methodology, and foundry teams.
  • Strong communication, ownership, problem-solving, and mentoring skills.

Preferred / Plus Qualifications

• Experience with memory compilers and production-quality memory IP.
• Experience with 5nm, 3nm, 2nm, or other advanced FinFET/GAA processes.
• Experience with layout automation, scripting, or custom layout productivity tools.
• Exposure to AI-assisted IC layout or semiconductor design automation tools.
• Experience developing reusable layout methodologies and automation frameworks.