High-Performance SRAM Design and Layout Engineer

QUALCOMM, Inc.; Santa Clara (CA); Hybrid; USD 148,000 - 222,000; Full time

Job summary

Qualcomm Technologies, Inc. in Santa Clara seeks an experienced CPU SRAM Design & Layout Engineer to own memory development from schematic to signoff.

You will design high-performance, power-efficient SRAMs and register files, create schematics, floorplans, and layouts, and collaborate with CAD and physical design teams to deliver manufacturable solutions. The role emphasizes memory architecture, layout verification (LVS/DRC), timing and power analysis, and contribution to DFT/automation.

Qualifications

• Bachelor's degree in Electrical Engineering or related field with 5+ years of relevant industry experience
• OR Master's degree in Electrical Engineering with 2+ years of relevant industry experience
• Experience designing custom SRAM circuits and register files
• Experience with custom memory layout design and implementation
• Experience using industry-standard custom design tools and methodologies
• Experience with circuit simulation, Monte Carlo analysis, and static timing analysis
• Knowledge of advanced semiconductor technologies, including FinFET and nanosheet process nodes
• Experience with deep sub-micron layout design for memory, datapath, and standard cell circuits
• Knowledge of layout floorplanning, hierarchical assembly, and physical verification methodologies
• Experience with Cadence Virtuoso and Calibre LVS/DRC verification flows

Responsibilities

• Design and develop custom SRAM and register file circuits optimized for high performance, low power, and scalability
• Create schematics and perform circuit-level design and optimization
• Develop memory floorplans and custom layouts based on project requirements and schematics
• Own memory implementation from initial architecture and floorplanning through physical verification and signoff
• Perform and oversee layout construction, verification, and optimization
• Read and interpret process design rules to create robust, manufacturable layouts
• Execute and analyze LVS, DRC, ERC, and other physical verification checks
• Identify and resolve design, verification, and layout issues throughout the development process
• Perform functional verification, simulation, and margin analysis across process, voltage, and temperature conditions
• Perform timing, power, and electrical characterization of memory designs
• Generate and validate all required memory deliverables and collateral models
• Collaborate with CAD teams to improve modeling, automation, and characterization flows
• Work with Physical Design teams to resolve memory PPA challenges
• Provide layout guidance and physical implementation recommendations to improve circuit performance, reliability, and manufacturability
• Contribute to DFT, modeling, automation, and analysis flow development where applicable
• Develop realistic project schedules and independently drive memory design and implementation activities to completion
• Provide technical insight and recommendations regarding memory architecture, layout strategy, area optimization, and methodology improvements

Skills

SRAM design

Register file design

Memory layout

Circuit verification

Timing analysis

Cross-functional collaboration

Education

Bachelor0s degree in Electrical Engineering

Master0s degree in Electrical Engineering/CS

PhD in Electrical Engineering/CS

Tools

Cadence Virtuoso

Calibre LVS/DRC

NanoTime

Ansys EMIR

ESP-CV

Liberate

Scripting (SKILL)

Job description

Qualcomm Technologies, Inc. in Santa Clara seeks an experienced CPU SRAM Design & Layout Engineer to own memory development from schematic to signoff.

You will design high-performance, power-efficient SRAMs and register files, create schematics, floorplans, and layouts, and collaborate with CAD and physical design teams to deliver manufacturable solutions. The role emphasizes memory architecture, layout verification (LVS/DRC), timing and power analysis, and contribution to DFT/automation.