Senior SRAM Layout Architect (5nm/3nm)

Infobahn Softworld Inc; Santa Clara (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

NVIDIA's memory IP group seeks a Senior SRAM / Memory Custom Layout Engineer to lead full-custom layout for SRAM bitcells, memory periphery, and macros in advanced CMOS. You will collaborate with circuit design, CAD, and foundry teams to deliver tapeouts in FinFET/GAA nodes.

Requires a BSEE or equivalent, 10+ years in custom IC layout, 5+ years SRAM/memory IP layout, and expert Cadence Virtuoso usage; knowledge of Calibre/ICV for DRC/LVS is essential; contribute to layout methodologies and

Qualifications

• BSEE or equivalent technical experience.
• 10+ years of custom IC layout experience.
• 5+ years SRAM, memory IP layout experience.
• Strong experience with advanced CMOS technologies, FinFET/GAA 5nm/3nm+.
• Deep understanding SRAM and memory layout architectures.
• Extensive hands-on Cadence Virtuoso for custom layout.
• Strong experience debugging DRC/LVS with Calibre/ICV.
• Collaborate with circuit design, CAD, foundry teams.

Responsibilities

• Own the complete custom layout process for SRAM bitcell arrays, memory periphery, test structures, and memory macros.
• Develop and optimize floorplans for SRAM and memory blocks with power grids and routing channels.
• Create and debug custom layouts using Cadence Virtuoso.
• Resolve DRC, LVS, ERC, antenna, and physical verification issues using Calibre/ICV.
• Support EM/IR, power integrity, density/fill, DFM and tapeout requirements.
• Translate schematics into high-quality layouts while ensuring matching, symmetry, shielding.
• Collaborate with PnR/integration teams to address top-level issues.
• Develop layout methodologies, checklists, and reusable practices.

Skills

SRAM layout

Advanced CMOS layouts

Cadence Virtuoso

Floorplanning

DRC/LVS debugging

Mentoring

Education

BSEE or equivalent

Tools

Cadence Virtuoso

Calibre

ICV

Job description

NVIDIA's memory IP group seeks a Senior SRAM / Memory Custom Layout Engineer to lead full-custom layout for SRAM bitcells, memory periphery, and macros in advanced CMOS. You will collaborate with circuit design, CAD, and foundry teams to deliver tapeouts in FinFET/GAA nodes.

Requires a BSEE or equivalent, 10+ years in custom IC layout, 5+ years SRAM/memory IP layout, and expert Cadence Virtuoso usage; knowledge of Calibre/ICV for DRC/LVS is essential; contribute to layout methodologies and