Hardware / Lab Technician - Layout Design Engineer(739-1)

MetAntz; Santa Clara (CA); On-site; USD 180,000 - 280,000; Full time

Job summary

MetAntz is seeking a Senior Custom IC Layout Engineer to lead the full custom layout process for SRAM bitcell arrays and memory macros in advanced CMOS technologies. You will develop floorplans, perform physical verifications, and collaborate across CAD, foundry, and circuit teams to ensure high-quality memory IP delivery.

You will mentor engineers, improve layout methodology, and address top-level design challenges with a hands-on, detail-oriented approach in a fast-paced environment.

Qualifications

• BSEE or equivalent required.
• 10+ years of custom IC layout experience including SRAM/memory IP.
• Hands-on with FinFET/GAA at 5nm or smaller.
• Proficiency with Cadence Virtuoso for custom layout.
• Experience with DRC/LVS using Calibre/ICV.
• Ability to mentor engineers.

Responsibilities

• Manage the complete custom layout process for SRAM bitcell arrays, memory periphery, test structures, and memory macros in advanced CMOS technologies.
• Develop and improve floorplans for SRAM and memory blocks, covering array layout, periphery positioning, power grid design, routing channels, and macro assembly.
• Carry out, debug, and complete DRC, LVS, ERC, antenna, and related checks with tools such as Calibre, ICV, or similar workflows.
• Support EM, IR review, power integrity, density, fill, DFM, dummy insertion, layout-dependent effects, and tapeout requirements.
• Collaborate with circuit designers to convert schematics into layouts, ensuring matching, symmetry, shielding, parasitic targets, and reliability constraints.
• Collaborate with PnR and integration teams to resolve top-level DRC, LVS, pin access, boundary, routing, power-grid, and macro-integration issues.
• Implement and advance layout methodology, checklists, reusable practices, and quality standards for consistent memory IP delivery.
• Collaborate with foundry, CAD, and methodology teams on rule interpretation, deck behavior, waivers, and advanced-node process constraints.
• Review layouts, mentor junior engineers, and help raise layout quality and execution rigor across the team.

Skills

SRAM/memory IP layout

Floorplanning

Mentoring

Collaboration with CAD/Foundry

Leadership / ownership

Advanced-node FinFET/5nm

Layout automation / AI tools

Strong communication

Education

BSEE or equivalent

Tools

Cadence Virtuoso

Calibre/ICV

Job description

Senior Custom IC Layout Engineer

Roles and Responsibilities

• Manage the complete custom layout process for SRAM bitcell arrays, memory periphery, test structures, and memory macros in advanced CMOS technologies.
• Develop and improve floorplans for SRAM and memory blocks, covering array layout, periphery positioning, power grid design, routing channels, and macro assembly.
• Carry out, debug, and complete DRC, LVS, ERC, antenna, and associated physical verification checks with tools such as Calibre, ICV, or similar workflows.
• Support EM, IR review, power integrity, density, fill, DFM, dummy insertion, layout-dependent effects, and other requirements for tapeout.
• Collaborate with circuit designers to convert schematics into layouts, ensuring matching, symmetry, shielding, parasitic targets, and reliability constraints are maintained.
• Collaborate with PnR and integration teams to resolve top-level DRC, LVS, pin access, boundary, routing, power-grid, and macro-integration issues.
• Implement and advance layout methodology, checklists, reusable practices, and quality standards for consistent memory IP delivery.
• Collaborate with foundry, CAD, and methodology teams on rule interpretation, deck behavior, waivers, and advanced-node process constraints.
• Review layouts, mentor junior engineers, and help raise layout quality and execution rigor across the team.

Key Required Skills

• Have a BSEE or equivalent experience
• 10+ years of custom IC layout experience, including 5+ years in SRAM, memory compiler, or full‑custom memory IP layout.
• Hands‑on participation in advanced CMOS technology initiatives, preferably concentrating on FinFET or GAA nodes at 5nm, 3nm, or smaller dimensions.
• Solid grasp of SRAM and memory layout principles.
• Extensive experience in Cadence Virtuoso applied to custom layout creation and assessment.
• Extensive experience in DRC, LVS debugging using Calibre, ICV, or similar physical verification tools.
• Experience with floorplanning, block‑level routing, macro assembly, pin planning, boundary, interface management, and top‑level physical verification.
• Direct familiarity with advanced‑node layout limitations and layout‑dependent phenomena, including LOD, density, fill, matching, symmetry, shielding, electromigration, IR drop, and DFM or similar expertise.
• Ability to work effectively with circuit build, physical build, integration, CAD, and foundry teams.
• Clear communication, strong ownership, good judgment, and the ability to mentor other engineers.
• Knowledge of layout automation or AI tools is a definite plus. Location Santa Clara, California, USA