Senior SRAM Layout Architect for 5nm/3nm Memory IP

DGN Technologies Inc; Santa Clara (CA); On-site; USD 140,000 - 220,000; Full time

Job summary

DGN Technologies Inc in California seeks an experienced layout engineer to own the complete custom layout of SRAM bitcell arrays, memory periphery, and memory macros. You will partner with circuit designers to translate schematics into robust layouts and with P&R teams to ensure top-level integrity for tapeouts.

The role requires deep expertise in Cadence Virtuoso, DRC/LVS workflows (Calibre/ICV), and familiarity with advanced nodes (5nm/3nm).

Qualifications

• BSEE or equivalent experience required.
• 10+ years in custom IC layout.
• 5+ years in SRAM/memory IP layout.
• Experience with FinFET/GAA nodes (5nm/3nm).
• Proficient in Cadence Virtuoso and physical verification tools.

Responsibilities

• Manage complete custom layout process for SRAM bitcells and memory macros.
• Develop floorplans for SRAM and memory blocks, including power grid and routing.
• Perform DRC/LVS/ERC checks and debug with Calibre/ICV workflows.
• Collaborate with circuit, PnR, and integration teams to resolve top-level issues.
• Mentor junior engineers and promote layout quality and best practices.

Skills

Custom IC layout

SRAM memory IP layout

Cadence Virtuoso

Physical verification (DRC/LVS/ERC)

Floorplanning

FinFET/GAAs (5nm/3nm)

Pin planning & boundary management

Mentoring

Layout automation or AI tools

Cross-functional collaboration

Education

BSEE or equivalent

Tools

Cadence Virtuoso

Calibre/ICV

Job description

DGN Technologies Inc in California seeks an experienced layout engineer to own the complete custom layout of SRAM bitcell arrays, memory periphery, and memory macros. You will partner with circuit designers to translate schematics into robust layouts and with P&R teams to ensure top-level integrity for tapeouts.

The role requires deep expertise in Cadence Virtuoso, DRC/LVS workflows (Calibre/ICV), and familiarity with advanced nodes (5nm/3nm).