SRAM Design & Layout Engineer - High-Performance Memory

QUALCOMM, Inc.; Santa Clara (CA); On-site; USD 148,000 - 222,000; Full time

Job summary

Qualcomm Technologies, Inc. is seeking a CPU SRAM Design & Layout Engineer to own custom SRAM and register file memories from architecture through signoff. You will work with cross-functional teams to optimize performance, power, area, and reliability while delivering robust memory solutions.

The role emphasizes floorplanning, schematic capture, layout, verification, and model generation, with close collaboration with circuit and CAD teams.

Qualifications

• Bachelor's degree in Electrical Engineering or related field with 5+ years of relevant industry experience.
• Master's degree in Electrical Engineering with 2+ years of relevant industry experience.
• Experience designing custom SRAM circuits and register files.
• Experience with custom memory layout design and implementation.
• Knowledge of Cadence Virtuoso and Calibre LVS/DRC verification flows.

Responsibilities

• Design and develop custom SRAM and register file circuits optimized for high performance, low power, and scalability.
• Create schematics and perform circuit-level design and optimization.
• Develop memory floorplans and custom layouts based on project requirements and schematics.
• Own memory implementation from initial architecture and floorplanning through physical verification and signoff.
• Perform LVS, DRC, ERC checks and coordinate issue resolution across design/verification/layout teams.
• Collaborate with CAD/Physical Design teams to improve modeling, automation, and flows.

Job description

Qualcomm Technologies, Inc. is seeking a CPU SRAM Design & Layout Engineer to own custom SRAM and register file memories from architecture through signoff. You will work with cross-functional teams to optimize performance, power, area, and reliability while delivering robust memory solutions.

The role emphasizes floorplanning, schematic capture, layout, verification, and model generation, with close collaboration with circuit and CAD teams.