Sr. SRAM Layout Design Engineer supporting Nvidia

Sustainable Talent; Santa Clara (CA); On-site; USD 228,000 - 250,000; Full time

Benefits offered by this job

Full benefits

PTO

Job summary

Sustainable Talent is partnering with NVIDIA in Santa Clara, CA to recruit for a Senior SRAM Layout Design Engineer on-site. This full-time W-2 contract role offers competitive pay and full benefits.

You will own the complete custom SRAM layout process across bitcells, periphery, and macros in advanced CMOS nodes. Required are 10+ years in IC layout with SRAM/memory IP focus, hands-on use of Cadence Virtuoso, and strong collaboration with circuit, CAD, and foundry teams.

Qualifications

• BSEE or equivalent required.
• 10+ years in custom IC layout; 5+ years in SRAM/memory IP layout.
• Experience with FinFET/GAA nodes at 5nm/3nm.
• Proficient in Cadence Virtuoso for custom layout.
• DRC/LVS debugging with Calibre/ICV.

Responsibilities

• Manage SRAM layout from bitcells to macros.
• Develop floorplans and routing for SRAM/memory blocks.
• Perform DRC/LVS/ERC checks and layout verification.
• Support power integrity, density/fill, and tape-out requirements.
• Collaborate with circuit designers to translate schematics to layouts.

Skills

10+ years custom IC layout

SRAM layout experience

Memory IP layout

Team mentoring

Strong communication

Layout automation tools

Education

BSEE or equivalent

Tools

Cadence Virtuoso

Calibre

ICV

Job description

Sustainable Talent is partnering with NVIDIA, a global leader that has been transforming computer graphics, PC gaming, and accelerated computing for over 25 years. We are looking for a Senior SRAM Layout Design Engineer to support our client's team onsite in Santa Clara, CA.

Full-time (W-2) contract role. We offer competitive pay $110/hr - $120/hr based on factors like experience, education, location, etc. and provide full benefits, PTO, and amazing company culture!

What you'll do:

• Manage the complete custom layout process for SRAM (Static Random-Access Memory) bitcell arrays, memory periphery, test structures, and memory macros in advanced CMOS technologies.
• Develop and improve floorplans for SRAM and memory blocks, covering array layout, periphery positioning, power grid design, routing channels, and macro assembly.
• Carry out, debug, and complete DRC, LVS, ERC, antenna, and associated physical verification checks with tools such as Calibre, ICV, or similar workflows.
• Support EM/IR review, power integrity, density/fill, DFM, dummy insertion, layout-dependent effects, and other requirements for tape out.
• Collaborate with circuit designers to convert schematics into layouts, ensuring matching, symmetry, shielding, parasitic targets, and reliability constraints are maintained.
• Collaborate with PnR and integration teams to resolve top-level DRC/LVS, pin access, boundary, routing, power-grid, and macro-integration issues.
• Implement and advance layout methodology, checklists, reusable practices, and quality standards for consistent memory IP delivery.
• Collaborate with foundry, CAD, and methodology teams on rule interpretation, deck behavior, waivers, and advanced-node process constraints.
• Review layouts, mentor junior engineers, and help raise layout quality and execution rigor across the team.

Key required skills:

• Have a BSEE or equivalent experience
• 10+ years of custom IC layout experience, including 5+ years in SRAM, memory compiler, or full-custom memory IP layout.
• Hands-on participation in advanced CMOS technology initiatives, preferably concentrating on FinFET or GAA nodes at 5nm, 3nm, or smaller dimensions.
• Solid grasp of SRAM and memory layout principles.
• Extensive experience in Cadence Virtuoso applied to custom layout creation and assessment.
• Extensive experience in DRC/LVS debugging using Calibre, ICV, or similar physical verification tools.
• Experience with floor planning, block-level routing, macro assembly, pin planning, boundary/interface management, and top-level physical verification.
• Direct familiarity with advanced-node layout limitations and layout-dependent phenomena, including LOD, density/fill, matching, symmetry, shielding, electromigration, IR drop, and DFM or similar expertise.
• Ability to work effectively with circuit build, physical build, integration, CAD, and foundry teams.
• Clear communication, strong ownership, good judgment, and the ability to mentor other engineers.
• Knowledge of layout automation or AI tools is a definite plus.

Sustainable Talent is a M/F+, disabled, and veteran equal employment opportunity and affirmative action employer.

Sustainable Talent's Equal Employment Opportunity policy, we do not discriminate on the basis of any protected group status under any applicable law.