Senior SRAM Layout Design Engineer

DGN Technologies Inc; Santa Clara (CA); On-site; USD 140,000 - 220,000; Full time

Job summary

DGN Technologies Inc in California seeks an experienced layout engineer to own the complete custom layout of SRAM bitcell arrays, memory periphery, and memory macros. You will partner with circuit designers to translate schematics into robust layouts and with P&R teams to ensure top-level integrity for tapeouts.

The role requires deep expertise in Cadence Virtuoso, DRC/LVS workflows (Calibre/ICV), and familiarity with advanced nodes (5nm/3nm).

Qualifications

• BSEE or equivalent experience required.
• 10+ years in custom IC layout.
• 5+ years in SRAM/memory IP layout.
• Experience with FinFET/GAA nodes (5nm/3nm).
• Proficient in Cadence Virtuoso and physical verification tools.

Responsibilities

• Manage complete custom layout process for SRAM bitcells and memory macros.
• Develop floorplans for SRAM and memory blocks, including power grid and routing.
• Perform DRC/LVS/ERC checks and debug with Calibre/ICV workflows.
• Collaborate with circuit, PnR, and integration teams to resolve top-level issues.
• Mentor junior engineers and promote layout quality and best practices.

Skills

Custom IC layout

SRAM memory IP layout

Cadence Virtuoso

Physical verification (DRC/LVS/ERC)

Floorplanning

FinFET/GAAs (5nm/3nm)

Pin planning & boundary management

Mentoring

Layout automation or AI tools

Cross-functional collaboration

Education

BSEE or equivalent

Tools

Cadence Virtuoso

Calibre/ICV

Job description

• · Manage the complete custom layout process for SRAM bitcell arrays, memory periphery, test structures, and memory macros in advanced CMOS technologies.
• · Develop and improve floorplans for SRAM and memory blocks, covering array layout, periphery positioning, power grid design, routing channels, and macro assembly.
• · Carry out, debug, and complete DRC, LVS, ERC, antenna, and associated physical verification checks with tools such as Calibre, ICV, or similar workflows.
• · Support EM/IR review, power integrity, density/fill, DFM, dummy insertion, layout-dependent effects, and other requirements for tapeout.
• · Collaborate with circuit designers to convert schematics into layouts, ensuring matching, symmetry, shielding, parasitic targets, and reliability constraints are maintained.
• · Collaborate with PnR and integration teams to resolve top-level DRC/LVS, pin access, boundary, routing, power-grid, and macro-integration issues.
• · Implement and advance layout methodology, checklists, reusable practices, and quality standards for consistent memory IP delivery.
• · Collaborate with foundry, CAD, and methodology teams on rule interpretation, deck behavior, waivers, and advanced-node process constraints.
• · Review layouts, mentor junior engineers, and help raise layout quality and execution rigor across the team.

Key required skills:

• · Have a BSEE or equivalent experience
• · 10+ years of custom IC layout experience, including 5+ years in SRAM, memory compiler, or full-custom memory IP layout.
• · Hands-on participation in advanced CMOS technology initiatives, preferably concentrating on FinFET or GAA nodes at 5nm, 3nm, or smaller dimensions.
• · Solid grasp of SRAM and memory layout principles.
• · Extensive experience in Cadence Virtuoso applied to custom layout creation and assessment.
• · Extensive experience in DRC/LVS debugging using Calibre, ICV, or similar physical verification tools.
• · Experience with floorplanning, block-level routing, macro assembly, pin planning, boundary/interface management, and top-level physical verification.
• · Direct familiarity with advanced-node layout limitations and layout-dependent phenomena, including LOD, density/fill, matching, symmetry, shielding, electromigration, IR drop, and DFM or similar expertise.
• · Ability to work effectively with circuit build, physical build, integration, CAD, and foundry teams.
• · Clear communication, strong ownership, good judgment, and the ability to mentor other engineers.
• · Knowledge of layout automation or AI tools is a definite plus.