Senior SRAM Layout Architect – Advanced Memory IP

Sustainable Talent; Santa Clara (CA); On-site; USD 228,000 - 250,000; Full time

Benefits offered by this job

Full benefits

PTO

Job summary

Sustainable Talent is partnering with NVIDIA in Santa Clara, CA to recruit for a Senior SRAM Layout Design Engineer on-site. This full-time W-2 contract role offers competitive pay and full benefits.

You will own the complete custom SRAM layout process across bitcells, periphery, and macros in advanced CMOS nodes. Required are 10+ years in IC layout with SRAM/memory IP focus, hands-on use of Cadence Virtuoso, and strong collaboration with circuit, CAD, and foundry teams.

Qualifications

• BSEE or equivalent required.
• 10+ years in custom IC layout; 5+ years in SRAM/memory IP layout.
• Experience with FinFET/GAA nodes at 5nm/3nm.
• Proficient in Cadence Virtuoso for custom layout.
• DRC/LVS debugging with Calibre/ICV.

Responsibilities

• Manage SRAM layout from bitcells to macros.
• Develop floorplans and routing for SRAM/memory blocks.
• Perform DRC/LVS/ERC checks and layout verification.
• Support power integrity, density/fill, and tape-out requirements.
• Collaborate with circuit designers to translate schematics to layouts.

Skills

10+ years custom IC layout

SRAM layout experience

Memory IP layout

Team mentoring

Strong communication

Layout automation tools

Education

BSEE or equivalent

Tools

Cadence Virtuoso

Calibre

ICV

Job description

Sustainable Talent is partnering with NVIDIA in Santa Clara, CA to recruit for a Senior SRAM Layout Design Engineer on-site. This full-time W-2 contract role offers competitive pay and full benefits.

You will own the complete custom SRAM layout process across bitcells, periphery, and macros in advanced CMOS nodes. Required are 10+ years in IC layout with SRAM/memory IP focus, hands-on use of Cadence Virtuoso, and strong collaboration with circuit, CAD, and foundry teams.