Senior SRAM Layout Engineer — Advanced Node Memory IP

Gdh Consulting, Inc.; Santa Clara (CA); On-site; USD 101,000 - 106,000; Full time

Benefits offered by this job

Medical insurance

Dental & Vision insurance

Life insurance

401(k)

Wellbeats membership

Gym membership discount

Job summary

GDH Consulting, Inc. is seeking a senior SRAM layout design engineer to take full ownership of the custom layout process for SRAM bitcell arrays, peripheries, and memory macros on advanced CMOS nodes.

The role emphasizes layout quality, parasitic control, and collaboration with circuit and CAD teams. You will develop floorplans, perform DRC/LVS/ERC checks, and support tapeout readiness, while mentoring junior engineers and refining layout methodologies.

Qualifications

• Bachelor's degree in Electrical Engineering or equivalent.
• Over 10 years of IC layout experience with at least 5 years in SRAM/memory IP layout.
• Experience executing custom SRAM layouts, not just reviews.
• Deep experience with 3nm or newer nodes; 5nm a plus.
• Strong understanding of LOD, density, fill, masking, and electromigration.
• Proficiency in Cadence Virtuoso and DRC/LVS debugging with Calibre/ICV.
• Ability to collaborate with circuit, PnR, foundry, and CAD teams.
• Authorized to work in the United States without sponsorship.

Responsibilities

• Manage the complete custom layout process for SRAM bitcell arrays, peripheries, test structures, and memory macros utilizing advanced CMOS technologies.
• Develop and optimize floorplans for memory arrays, including placement, power grid design, routing channels, and macro assembly.
• Perform, debug, and complete DRC/LVS/ERC and other checks with tools like Calibre and ICV.
• Support parasitic extraction, EM and IR drop analysis, power integrity, density/fill and layout‑dependent effects for tapeout.
• Collaborate with circuit designers to translate schematics into layouts with matching, symmetry, shielding and reliability.
• Coordinate with front‑end design, PnR and integration teams to resolve top‑level layout issues and pin access.
• Develop and refine layout methodologies, checklists, and best practices for high‑quality memory IP.
• Partner with foundry, CAD, and methodology teams to interpret design rules and constraints for advanced nodes.
• Review layouts and mentor junior engineers to raise layout quality and process rigor.

Skills

Strong communication

Mentorship

Ownership

Team collaboration

Education

Bachelor's degree in Electrical Engineering or equivalent

Tools

Cadence Virtuoso

Calibre

ICV

Job description

GDH Consulting, Inc. is seeking a senior SRAM layout design engineer to take full ownership of the custom layout process for SRAM bitcell arrays, peripheries, and memory macros on advanced CMOS nodes.

The role emphasizes layout quality, parasitic control, and collaboration with circuit and CAD teams. You will develop floorplans, perform DRC/LVS/ERC checks, and support tapeout readiness, while mentoring junior engineers and refining layout methodologies.