Senior SRAM Layout Designer for Advanced Memory IP

Akkodis

Fremont (CA)

On-site

USD 138,000 - 152,000

Full time

14 days+

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Job summary

Akkodis is seeking an experienced Senior SRAM Layout Design Engineer to join a world-class semiconductor team in Santa Clara, CA on a contract basis. You will own the complete custom layout development of SRAM bitcell arrays, memory periphery, and memory macros, including floorplanning and top-level verification.

Required: 10+ years in Custom IC Layout, Cadence Virtuoso, Calibre/ICV experience, and strong floorplanning skills.

Qualifications

Bachelor's degree in Electrical Engineering (BSEE) or equivalent experience.
10+ years of Custom IC Layout experience.
5+ years of hands-on SRAM Layout Design.

Responsibilities

Own the complete custom layout development of SRAM bitcell arrays, memory periphery, test structures, and memory macros.
Create and optimize floorplans for SRAM and memory blocks, including array layout, peripheral circuits, power grids, routing channels, and macro assembly.
Perform and debug physical verification including DRC, LVS, ERC, antenna, and related checks using Calibre, ICV, or similar tools.
Support tapeout readiness through EM/IR analysis, density/fill, DFM, dummy fill insertion, layout-dependent effect mitigation, and reliability verification.
Partner with circuit designers to translate schematics into high-quality layouts meeting matching, symmetry, shielding, parasitic, and reliability requirements.