Senior SRAM Layout Design Engineer

DGN Technologies; Santa Clara (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

DGN Technologies is seeking an experienced layout engineer to lead custom IC layout for SRAM and memory IP in advanced CMOS nodes. You will own floorplanning, routing, and top-level verification in collaboration with circuit, CAD, and foundry teams.

You will mentor engineers, advance layout methodologies, and ensure memory IP delivery meets tight reliability and performance targets in cutting-edge process nodes (5nm/3nm and below).

Qualifications

• BSEE or equivalent degree required.
• Ten years of custom IC layout experience preferred, with five+ years in SRAM/memory IP layout.
• Experience with advanced CMOS nodes (5nm/3nm or smaller) is highly desirable.

Responsibilities

• Manage complete custom layout for SRAM bitcell arrays, memory periphery, test structures, and memory macros.
• Develop floorplans for SRAM and memory blocks, including routing channels and power grid design.
• Perform DRC/LVS/ERC checks and physical verification using tools like Calibre/ICV.
• Support tapeout activities including power integrity, density/fill, and DFM considerations.
• Collaborate with circuit designers to translate schematics into layouts with matching and reliability constraints.
• Coordinate with PnR and integration teams to resolve top-level DRC/LVS and macro-integration issues.
• Mentor junior engineers and advance layout methodologies and best practices.

Skills

Floorplanning

Memory IP experience

Team collaboration

Education

BSEE or equivalent

10 years custom IC layout

SRAM/memory IP layout experience

Tools

Cadence Virtuoso

Calibre

ICV

Job description

Job description:

• Manage the complete custom layout process for SRAM bitcell arrays, memory periphery, test structures, and memory macros in advanced CMOS technologies.
• Develop and improve floorplans for SRAM and memory blocks, covering array layout, periphery positioning, power grid design, routing channels, and macro assembly.
• Carry out, debug, and complete DRC, LVS, ERC, antenna, and associated physical verification checks with tools such as Calibre, ICV, or similar workflows.
• Support EM/IR review, power integrity, density/fill, DFM, dummy insertion, layout-dependent effects, and other requirements for tapeout.
• Collaborate with circuit designers to convert schematics into layouts, ensuring matching, symmetry, shielding, parasitic targets, and reliability constraints are maintained.
• Collaborate with PnR and integration teams to resolve top-level DRC/LVS, pin access, boundary, routing, power-grid, and macro-integration issues.
• Implement and advance layout methodology, checklists, reusable practices, and quality standards for consistent memory IP delivery.
• Collaborate with foundry, CAD, and methodology teams on rule interpretation, deck behavior, waivers, and advanced-node process constraints.
• Review layouts, mentor junior engineers, and help raise layout quality and execution rigor across the team.

Key required skills:

• Have a BSEE or equivalent experience
• 10 years of custom IC layout experience, including 5 years in SRAM, memory compiler, or full-custom memory IP layout.
• Hands-on participation in advanced CMOS technology initiatives, preferably concentrating on FinFET or GAA nodes at 5nm, 3nm, or smaller dimensions.
• Solid grasp of SRAM and memory layout principles.
• Extensive experience in Cadence Virtuoso applied to custom layout creation and assessment.
• Extensive experience in DRC/LVS debugging using Calibre, ICV, or similar physical verification tools.
• Experience with floorplanning, block-level routing, macro assembly, pin planning, boundary/interface management, and top-level physical verification.
• Direct familiarity with advanced-node layout limitations and layout-dependent phenomena, including LOD, density/fill, matching, symmetry, shielding, electromigration, IR drop, and DFM or similar expertise.
• Ability to work effectively with circuit build, physical build, integration, CAD, and foundry teams.
• Clear communication, strong ownership, good judgment, and the ability to mentor other engineers.
• Knowledge of layout automation or AI tools is a definite plus.