Senior SRAM Layout Engineer — Advanced Memory IP

Sustainable-Talent; San Jose (CA); On-site; USD 315,195,000 - 343,849,000; Full time

Benefits offered by this job

Full benefits

PTO

Onsite in Santa Clara

Job summary

Sustainable Talent is partnering with NVIDIA to recruit a Senior SRAM Layout Design Engineer for the client team onsite in Santa Clara, CA.

This is a full-time (W-2) contract role. We offer competitive pay $110/hr - $120/hr based on experience, education, location, etc., and provide full benefits, PTO, and a great company culture!

You will manage SRAM layout, floorplanning, DRC/LVS checks, and collaborate with circuit, PnR, and foundry teams to ensure robust memory IP delivery.

Qualifications

• BSEE or equivalent experience.
• 10+ years of custom IC layout experience, including 5+ years in SRAM, memory IP layout.
• Hands-on participation in advanced CMOS tech initiatives, preferably FinFET/GAA at 5nm, 3nm or smaller.
• Solid grasp of SRAM and memory layout principles.
• Extensive experience in Cadence Virtuoso applied to custom layout creation and assessment.
• Extensive experience in DRC/LVS debugging using Calibre, ICV, or similar tools.
• Experience with floor planning, block-level routing, macro assembly, pin planning, boundary management, and top-level verification.
• Familiarity with advanced-node layout limitations and layout-dependent phenomena (LOD, density/fill, matching, shielding, EM, IR drop).
• Ability to work with circuit, CAD, foundry, and integration teams.
• Strong communication, ownership, and mentoring abilities.
• Knowledge of layout automation or AI tools is a plus.

Responsibilities

• Manage the complete custom layout process for SRAM bitcell arrays, periphery, test structures, and memory macros in advanced CMOS techs.
• Develop and improve floorplans for SRAM and memory blocks, including array layout and power-grid design.
• Carry out and debug DRC, LVS, ERC, antenna checks with Calibre, ICV, or similar workflows.
• Support EM/IR reviews, power integrity, density/fill, DFM, and tape-out requirements.
• Collaborate with circuit designers to convert schematics into layouts with matching and reliability targets.
• Coordinate with PnR and integration teams to resolve top-level DRC/LVS, pin access, and routing issues.
• Advance layout methodologies, checklists, and reusable practices for consistent memory IP delivery.
• Work with foundry, CAD, and methodology teams on rules, deck behavior, waivers, and process constraints.
• Review layouts and mentor junior engineers to raise quality and execution standards.

Skills

SRAM layout

Custom IC layout

Cadence Virtuoso

DRC/LVS debugging

Calibre/ICV

Floorplanning

Power integrity

Layout automation

Team collaboration

Mentoring

Education

BSEE or equivalent experience

Tools

Calibre

ICV

Job description

Sustainable Talent is partnering with NVIDIA to recruit a Senior SRAM Layout Design Engineer for the client team onsite in Santa Clara, CA.

This is a full-time (W-2) contract role. We offer competitive pay $110/hr - $120/hr based on experience, education, location, etc., and provide full benefits, PTO, and a great company culture!

You will manage SRAM layout, floorplanning, DRC/LVS checks, and collaborate with circuit, PnR, and foundry teams to ensure robust memory IP delivery.