Senior SRAM Layout Architect - CMOS 5nm/3nm

DGN Technologies; Santa Clara (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

DGN Technologies is seeking an experienced layout engineer to lead custom IC layout for SRAM and memory IP in advanced CMOS nodes. You will own floorplanning, routing, and top-level verification in collaboration with circuit, CAD, and foundry teams.

You will mentor engineers, advance layout methodologies, and ensure memory IP delivery meets tight reliability and performance targets in cutting-edge process nodes (5nm/3nm and below).

Qualifications

• BSEE or equivalent degree required.
• Ten years of custom IC layout experience preferred, with five+ years in SRAM/memory IP layout.
• Experience with advanced CMOS nodes (5nm/3nm or smaller) is highly desirable.

Responsibilities

• Manage complete custom layout for SRAM bitcell arrays, memory periphery, test structures, and memory macros.
• Develop floorplans for SRAM and memory blocks, including routing channels and power grid design.
• Perform DRC/LVS/ERC checks and physical verification using tools like Calibre/ICV.
• Support tapeout activities including power integrity, density/fill, and DFM considerations.
• Collaborate with circuit designers to translate schematics into layouts with matching and reliability constraints.
• Coordinate with PnR and integration teams to resolve top-level DRC/LVS and macro-integration issues.
• Mentor junior engineers and advance layout methodologies and best practices.

Skills

Floorplanning

Memory IP experience

Team collaboration

Education

BSEE or equivalent

10 years custom IC layout

SRAM/memory IP layout experience

Tools

Cadence Virtuoso

Calibre

ICV

Job description

DGN Technologies is seeking an experienced layout engineer to lead custom IC layout for SRAM and memory IP in advanced CMOS nodes. You will own floorplanning, routing, and top-level verification in collaboration with circuit, CAD, and foundry teams.

You will mentor engineers, advance layout methodologies, and ensure memory IP delivery meets tight reliability and performance targets in cutting-edge process nodes (5nm/3nm and below).