Senior SRAM Layout Design Engineer

Akkodis; Fremont (CA); On-site; USD 138,000 - 152,000; Full time

Job summary

Akkodis is seeking an experienced Senior SRAM Layout Design Engineer to join a world-class semiconductor team in Santa Clara, CA on a contract basis. You will own the complete custom layout development of SRAM bitcell arrays, memory periphery, and memory macros, including floorplanning and top-level verification.

Required: 10+ years in Custom IC Layout, Cadence Virtuoso, Calibre/ICV experience, and strong floorplanning skills.

Qualifications

• Bachelor's degree in Electrical Engineering (BSEE) or equivalent experience.
• 10+ years of Custom IC Layout experience.
• 5+ years of hands-on SRAM Layout Design.

Responsibilities

• Own the complete custom layout development of SRAM bitcell arrays, memory periphery, test structures, and memory macros.
• Create and optimize floorplans for SRAM and memory blocks, including array layout, peripheral circuits, power grids, routing channels, and macro assembly.
• Perform and debug physical verification including DRC, LVS, ERC, antenna, and related checks using Calibre, ICV, or similar tools.
• Support tapeout readiness through EM/IR analysis, density/fill, DFM, dummy fill insertion, layout-dependent effect mitigation, and reliability verification.
• Partner with circuit designers to translate schematics into high-quality layouts meeting matching, symmetry, shielding, parasitic, and reliability requirements.

Skills

SRAM Layout Design

Memory IP Layout

Floorplanning

Top-level verification

Education

BSEE

Tools

Cadence Virtuoso

Calibre

ICV

Job description

At Akkodis, we use our insight, knowledge, and global resources to make exceptional connections every day. With 60 branch offices located strategically throughout North America, we are positioned perfectly to deliver the industry's top talent to each of our clients. Clients choose Akkodis as their workforce partner to solve staffing challenges that range from locating hard-to-find niche talent to completing quick-fill demands.

Akkodis is seeking an Senior SRAM Layout Design Engineer for a contract role with a client located in Santa Clara, CA

Pay Rate: $100-$110/hr. (Hourly wage may be negotiable based upon experience, education, geographic location, and other factors)

Summary :

We're seeking an experienced Senior SRAM Layout Design Engineer to join a world-class semiconductor team focused on developing advanced memory IP for cutting-edge process technologies.

Responsibilities

• Own the complete custom layout development of SRAM bitcell arrays, memory periphery, test structures, and memory macros.
• Create and optimize floorplans for SRAM and memory blocks, including array layout, peripheral circuits, power grids, routing channels, and macro assembly.
• Perform and debug physical verification including DRC, LVS, ERC, antenna, and related checks using Calibre, ICV, or similar tools.
• Support tapeout readiness through EM/IR analysis, density/fill, DFM, dummy fill insertion, layout-dependent effect mitigation, and reliability verification.
• Partner closely with circuit designers to translate schematics into high-quality layouts while meeting matching, symmetry, shielding, parasitic, and reliability requirements.
• Work with integration and physical design teams to resolve top-level DRC/LVS, routing, power-grid, boundary, and macro integration challenges.
• Contribute to layout methodologies, reusable design practices, and quality standards to improve memory IP development efficiency.
• Collaborate with foundry, CAD, and methodology teams on advanced process-node requirements, design rules, and verification flows.
• Review layouts, mentor junior engineers, and help drive layout excellence across the team.

Required Qualifications

• Bachelor's degree in Electrical Engineering (BSEE) or equivalent experience.
• 10+ years of Custom IC Layout experience.
• 5+ years of hands-on experience in:
• SRAM Layout Design
• Memory Compiler Layout
• Memory Macro Development
• Memory IP Layout
• Strong understanding of digital SRAM and memory layout architectures.
• Expertise with Cadence Virtuoso for custom layout development.
• Extensive experience with Calibre, ICV, or similar physical verification tools.
• Proven experience in floorplanning, block-level routing, macro assembly, pin planning, and top-level physical verification.
• Experience with advanced-node layout challenges including:
• DFM
• Matching & Symmetry
• Shielding
• EM/IR
• Layout-Dependent Effects (LDE/LOD)

Preferred Qualifications

• Recent experience with TSMC advanced nodes, ideally:
• 3nm (N3)
• 2nm and below
• Experience with FinFET and/or GAA technologies.
• Knowledge of layout automation, scripting, or AI-assisted design tools.
• Strong communication skills and ability to work cross-functionally with circuit design, CAD, physical design, integration, and foundry teams.

Ideal Candidate

• Strong background in Digital SRAM Layout Design.
• Recent experience with advanced TSMC process nodes.
• Able to work independently and contribute immediately with minimal ramp-up.
• Experience delivering SRAM memory macros from layout through tapeout.

If you are interested in this Senior SRAM Layout Design Engineer then please click APPLY NOW. For other opportunities available at Akkodis go to www.akkodis.com. If you have questions about the position, please contact Priyanka Khurana at [e-mail]

Equal Opportunity Employer/Veterans/Disabled

Military connected talent encouraged to apply

Benefit offerings available for our associates include medical, dental, vision, life insurance, short-term disability, additional voluntary benefits, EAP program, commuter benefits and a 401K plan. Our benefit offerings provide employees the flexibility to choose the type of coverage that meets their individual needs. In addition, our associates may be eligible for paid leave including Paid Sick Leave or any other paid leave required by Federal, State, or local law, as well as Holiday pay where applicable.

To read our Candidate Privacy Information Statement, which explains how we will use your information, please visit https://www.modis.com/en-us/candidate-privacy/

The Company will consider qualified applicants with arrest and conviction records in accordance with federal, state, and local laws and/or security clearance requirements, including, as applicable:

• The California Fair Chance Act

• Los Angeles City Fair Chance Ordinance

• Los Angeles County Fair Chance Ordinance for Employers