Layout Design Engineer

Trinus Corporation; Santa Clara (CA); On-site; USD 180,000 - 260,000; Full time

Job summary

Trinus Corporation in Santa Clara, California seeks an experienced IC layout engineer to manage complete custom layout for SRAM and memory IP in advanced CMOS nodes. You will drive layout planning, ensure symmetry and reliability, and collaborate closely with circuit designers and PnR teams.

Join a team focused on high-quality memory IP delivery, mentoring engineers, advancing layout methodology, and ensuring successful tape-out with cutting-edge process nodes.

Qualifications

• BSEE or equivalent required.
• 10+ years in custom IC layout.
• 5+ years SRAM/memory IP layout.
• Experience with CMOS FinFET/GAA nodes.
• Proficiency with Cadence Virtuoso.
• Strong debugging with Calibre/ICV.

Responsibilities

• Develop and improve SRAM and memory layouts.
• Mentor junior engineers and review layouts.
• Collaborate with PnR, CAD, and foundry teams.
• Perform DRC/LVS/ER checks and optimize density.
• Lead layout validation for tape-out readiness.

Skills

IC layout

SRAM memory

Cadence Virtuoso

DRC/LVS debugging

Floor planning

Physical verification

FinFET/GAA

Cross-functional collab

Education

BSEE or equivalent

Tools

Calibre

ICV

Job description

Manage the complete custom layout process for SRAM Bitcell arrays, memory periphery, test structures, and memory macros in advanced CMOS technologies.

• Develop and improve floor plans for SRAM and memory blocks, covering array layout, periphery positioning, power grid design, routing channels, and macro assembly.
• Carry out, debug, and complete DRC, LVS, ERC, antenna, and associate physical verification check with tools such as Calibre, ICV, or similar workflows.
• Support EM/IR review, power integrity, density/fill, DFM, dummy insertion, layout-dependent effects, and other requirements for Tape out.
• Collaborate with circuit designers to convert schematics into layouts, ensuring matching, symmetry, shielding, parasitic targets, and reliability constraints are maintained.
• Collaborate with PnR and integration teams to resolve top-level DRC/LVS, pin access, boundary, routing, power-grid, and macro-integration issues.
• Implement and advance layout methodology, checklists, reusable practices, and quality standards for consistent memory IP delivery.
• Collaborate with foundry, CAD, and methodology teams on rule interpretation, deck behavior, waivers, and advanced-node process constraints.
• Review layouts, mentor junior engineers, and help raise layout quality and execution rigor across the team.

KEY REQUIRED SKILLS:

• Have a BSEE or equivalent experience.
• 10+ years of custom IC layout experience, including 5+ years in SRAM, memory compiler, or full-custom memory IP layout.
• Hands-on participation in advanced CMOS technology initiatives, preferably concentrating on FinFET or GAA nodes at 5nm, 3nm, or smaller dimensions.
• Solid grasp of SRAM and memory layout principles.
• Extensive experience in Cadence Virtuoso applied to custom layout creation and assessment.
• Extensive experience in DRC/LVS debugging using Calibre, ICV, or similar physical verification tools.
• Experience with floor planning, block-level routing, macro assembly, pin planning, boundary/interface management, and top-level physical verification.
• Direct familiarity with advanced-node layout limitations and layout-dependent phenomena, including LOD, density/fill, matching, symmetry, shielding, electromigration, IR drop, and DFM or similar expertise.
• Ability to work effectively with circuit build, physical build, integration, CAD, and foundry teams.
• Clear communication, strong ownership, good judgment, and the ability to mentor other engineers.

Knowledge of layout automation or AI tools is a definite plus.