SoC Verification Lead: System-Level, Flexible Work

Velaura AI, Inc.; Santa Clara (CA); On-site; USD 200,000 - 300,000; Full time

Job summary

Velaura AI, Inc. is seeking an experienced verification leader to own system level verification of the Physical AI SoC.

You will work with architects, RTL and software teams to ensure correctness, performance, reliability and safety of the design from RTL blocks to full systems running real workloads. You will define the verification plan, sign-off, and drive a small team, balancing hands-on coding with technical leadership across boot, clock/reset, low power, IO and memory subsystems, and

Qualifications

• 12+ years in design verification, including SoC-level experience.
• Experience leading SoC verification across multiple projects through sign-off and tape-out.
• Experience building and leading a verification team.
• Proficient in SystemVerilog, UVM, C/C++ with coverage-driven verification at system level.
• Experience managing simulation flows on CPU-based SoCs (ARM or RISC-V).
• Knowledge of IO/memory subsystems (PCIe, LPDDR5/LPDDR6).
• Experience verifying boot/root of trust, clock/reset topology, and low-power behavior at system level.

Responsibilities

• Own the SoC level verification strategy, plan and execution for the Velaura Physical AI SoC.
• Build and lead a team of SoC verification engineers, setting technical direction and reviewing their work.
• Define the SoC verification architecture and environment, and stay hands on in the code.
• Coordinate verification across boot and security, clock and reset, low power, and the IO and memory subsystems.
• Define sign off criteria and coverage goals, and drive closure through tape out.
• Track and report verification progress, coverage and risk to engineering leadership.
• Work with architecture, RTL, DFT, firmware and software teams on system level correctness and pre silicon bring up.
• Partner with CAD and infrastructure teams on simulation, emulation and regression capacity.

Skills

SoC verification leadership

SystemVerilog

UVM

C/C++

sign-off & tape-out planning

communication across disciplines

Tools

Simulation flows (ARM/RISC-V)

Emulation

FPGA prototyping

Job description

Velaura AI, Inc. is seeking an experienced verification leader to own system level verification of the Physical AI SoC.

You will work with architects, RTL and software teams to ensure correctness, performance, reliability and safety of the design from RTL blocks to full systems running real workloads. You will define the verification plan, sign-off, and drive a small team, balancing hands-on coding with technical leadership across boot, clock/reset, low power, IO and memory subsystems, and