Senior Emulation Architect for Next-Gen AI SoC

Velaura; Santa Clara (CA); On-site; USD 200,000 - 500,000; Full time

Job summary

Velaura is seeking a Senior Emulation Engineer to own and scale the emulation infrastructure for its next-generation Physical AI SoC. You will set up flows on Palladium, Veloce, and Zebu and partner with architects, RTL, verification, and software teams to accelerate pre-silicon validation.

You will bring up designs on emulators, optimize regression flows, and support HW/SW co-verification—firmware, drivers, runtime, and OS.

Qualifications

• 10+ years in hardware emulation or verification of complex digital systems.
• Hands-on experience with Palladium, Veloce, or Zebu emulation platforms.
• Ability to debug compile and elaboration issues on emulation platforms.
• Experience building emulation regression flows for faster turnaround.
• Strong analytical and problem-solving skills.
• Solid understanding of CPU/GPU/SoC architectures and digital design fundamentals.
• Experience with SystemVerilog, UVM, C/C++, transactors, and assertions.
• Experience debugging complex system-level issues across hardware and software.
• Strong scripting and automation for build, regression, and CI pipelines.
• Ability to work effectively in a multidisciplinary team.

Responsibilities

• Set up, own, and maintain emulation flows for the Velaura SoC on Palladium, Veloce, and/or Zebu.
• Bring up designs on the emulator, resolving compile/elaboration, capacity/partitioning, and design-mapping issues.
• Build and maintain regression flows, optimizing compile time, run time, throughput, and capacity utilization.
• Support HW/SW co-verification and pre-silicon software bring-up—firmware, drivers, runtime, and OS.
• Optimize on-emulator debug (waveform capture, triggers, visibility) and drive fast root-cause analysis across HW/SW.
• Verify performance, latency, bandwidth, QoS, and real-time behavior under representative workloads.
• Partner with architects, RTL, and verification engineers on emulation strategy, transactor requirements, and coverage goals.
• Emulate compute engines, memory subsystems, interconnect fabrics, control processors, DMA engines, and other coreSoC infrastructure.
• Build automation, scripting, and CI hooks for compile and regression pipelines.
• Contribute to FPGA prototyping, pre-silicon validation, and post-silicon debug.
• Apply modern tools, including AI-assisted verification and debug, to improve productivity, quality, and coverage.
• Contribute to a culture of technical excellence and continuous improvement.

Skills

Hardware emulation

Emulation flow setup

SystemVerilog/UVM

C/C++

Debugging complex systems

Multidisciplinary collaboration

Pre-silicon validation

Performance analysis

Tools

Palladium

Veloce

Zebu

AI-assisted verification tools

Job description

Velaura is seeking a Senior Emulation Engineer to own and scale the emulation infrastructure for its next-generation Physical AI SoC. You will set up flows on Palladium, Veloce, and Zebu and partner with architects, RTL, verification, and software teams to accelerate pre-silicon validation.

You will bring up designs on emulators, optimize regression flows, and support HW/SW co-verification—firmware, drivers, runtime, and OS.