Senior Verification Engineer - AI SoC & HW/SW Co-Validation

Velaura AI, Inc.; Santa Clara (CA); On-site; USD 200,000 - 300,000; Full time

Job summary

Velaura AI, Inc. in Santa Clara, CA is seeking Design Verification Engineers to verify next-generation Physical AI SoC architectures.

You will work with architects, RTL and software teams to validate complex hardware blocks and system-level behavior across the platform. You will help ensure correctness, performance, reliability and safety from RTL to HW/SW systems running real-world workloads, with opportunities to apply AI-assisted verification and pre-silicon bring-up practices in a

Qualifications

• 10+ Years of experience verifying complex digital systems.
• Strong analytical and problem-solving skills.
• Strong understanding of computer architecture, microarchitecture, SoC architecture and digital design fundamentals.
• Experience in understanding low power methodologies and verification criteria.
• Strong understanding of CDC issues, clocking and reset verification.
• Experience with SystemVerilog, UVM, C/C++, assertions, coverage-driven verification, and related methodologies.
• Familiarity with formal verification techniques and tools.
• Experience with emulation, FPGA prototyping, or pre-silicon validation environments.
• Understanding of memory systems, interconnect fabrics, caches, DMA engines, processors, or accelerator architectures.
• Experience debugging complex system-level issues.
• Ability to work effectively in a collaborative, multidisciplinary engineering environment.

Responsibilities

• Develop and execute verification strategies for key portions of the SoC.
• Build verification environments using SystemVerilog, UVM, C/C++, assertions, formal verification, emulation, and related methodologies.
• Collaborate with architects and RTL engineers to define verification plans, coverage goals, and correctness criteria.
• Verify compute engines, memory subsystems, interconnect fabrics, control processors, DMA engines, and other critical SoC infrastructure.
• Perform HW/SW co-verification involving firmware, drivers, runtime software, and operating system interactions.
• Verify performance, latency, bandwidth, QoS, and real-time system behavior under representative workloads.
• Develop assertions, checkers, scoreboards, and automated verification infrastructure.
• Participate in emulation, FPGA prototyping, and pre-silicon software bring-up activities.
• Drive bug investigation, root-cause analysis, and debug across hardware and software boundaries.
• Post-silicon debug and root cause analysis.
• Leverage modern engineering tools, including AI-assisted verification workflows, to improve productivity, quality, and coverage.

Skills

SystemVerilog

UVM

C/C++

Verification

Debugging

Collaboration

Problem solving

Tools

Emulation

FPGA prototyping

Formal verification

Assertions

Coverage-driven verification

Pre-silicon validation

Job description

Velaura AI, Inc. in Santa Clara, CA is seeking Design Verification Engineers to verify next-generation Physical AI SoC architectures.

You will work with architects, RTL and software teams to validate complex hardware blocks and system-level behavior across the platform. You will help ensure correctness, performance, reliability and safety from RTL to HW/SW systems running real-world workloads, with opportunities to apply AI-assisted verification and pre-silicon bring-up practices in a