Senior CPU Verification Engineer - High-Performance SoC

Velaura AI, Inc.; Santa Clara (CA); On-site; USD 200,000 - 300,000; Full time

Job summary

Velaura is seeking a Design Verification Engineer to verify and deliver the next generation Physical AI SoC. You will work closely with architects, RTL engineers, software teams and system groups to establish confidence in the correctness, performance, reliability and safety of the design, from RTL blocks to full hardware/software systems running real workloads.

This role focuses on our custom CPU. You will own a functional domain of its verification from test plan through coverage closure,

Qualifications

• 8 or more years verifying high performance CPUs or complex digital designs.
• Strong computer architecture and microarchitecture fundamentals.
• Experience with SystemVerilog, UVM, C and C++, assertions and coverage driven verification.
• Experience owning a block or unit of a design independently from test plan through coverage closure.
• Experience writing test plans, portable testbenches and transactors.
• Experience debugging complex issues across hardware and software boundaries.
• BS or higher in Computer Engineering, Electrical Engineering or Computer Science.
• Ability to work effectively in a collaborative multidisciplinary engineering environment.

Responsibilities

• Own verification of custom CPU units including instruction fetch, decode, load store, and the instruction, data and last level caches.
• Work with CPU and SoC architects to understand the intent behind a newly designed microarchitecture and turn it into detailed test and coverage plans.
• Build verification environments using SystemVerilog, UVM, C and C, with stimulus, checkers, assertions, trackers and coverage that stay portable across block and subsystem environments.
• Develop instruction level stimulus and compare against a golden instruction set simulator.
• Verify memory ordering, coherence, exceptions and privilege behavior against the architecture specification.
• Verify latency, bandwidth and cache behavior against high performance targets under representative workloads.
• Execute regressions through design and environment bring up, and track progress using bug and coverage metrics.
• Support emulation, FPGA prototyping and pre silicon software bring up, and drive root cause analysis across hardware and software boundaries.

Skills

CPU verification

SystemVerilog/UVM

C/C++

Test plan & coverage

Debugging across HW/SW

Collaborative engineering

Embedded/silicon bring-up

Education

Bachelor's degree in Computer Engineering, Electrical Engineering or Computer Science

Tools

SystemVerilog

UVM

C

C++

Simulator tools

Job description

Velaura is seeking a Design Verification Engineer to verify and deliver the next generation Physical AI SoC. You will work closely with architects, RTL engineers, software teams and system groups to establish confidence in the correctness, performance, reliability and safety of the design, from RTL blocks to full hardware/software systems running real workloads.

This role focuses on our custom CPU. You will own a functional domain of its verification from test plan through coverage closure,