Senior RTL Engineer - AI-SoC & High-Performance Hardware

Velaura; California (MO); On-site; USD 200,000 - 500,000; Full time

Job summary

Velaura is seeking a Senior RTL Engineer to help build its next-generation Physical AI SoC. You will partner with architects, performance modelers, software, verification and physical design teams to translate innovative concepts into production silicon.

You will own substantial RTL blocks, drive microarchitectural decisions, and optimize for high performance and power efficiency while supporting AI workloads and memory systems across the SoC.

Qualifications

• 8+ years designing RTL for complex digital systems with ownership of blocks through tapeout.
• Strong foundation in computer architecture and microarchitecture.
• Expert-level Verilog/SystemVerilog and RTL methodologies.
• Ability to make data-driven microarchitectural decisions.
• Experience with memory systems, interconnects, and DMA engines.

Responsibilities

• Own the design, implementation, and optimization of RTL for key portions of the Velaura SoC.
• Collaborate with architects to develop robust and efficient microarchitectures, and drive microarchitectural decisions within your areas of ownership.
• Participate in hardware/software co-design discussions spanning AI workloads, memory systems, runtime software, and system architecture.
• Work with software teams to define hardware interfaces, execution flows, memory hierarchies, and performance-critical interactions.
• Contribute to compute engines, memory subsystems, interconnect fabrics, control processors, DMA engines, power-management logic, and other core SoC infrastructure.
• Optimize designs for performance, power, area, scalability, and reliability.
• Partner closely with verification and physical design teams throughout the development cycle, and mentor junior engineers on design methodology and microarchitecture.
• Analyze performance bottlenecks and propose architectural and implementation improvements.
• Leverage modern engineering tools, including AI-assisted development workflows, to improve productivity, quality, and design exploration.
• Participate in and lead design reviews, contributing to a culture of technical excellence.

Skills

RTL design

Verilog/SystemVerilog

microarchitecture

performance optimization

problem-solving

Tools

EDA tools

Verilog tools

Job description

Velaura is seeking a Senior RTL Engineer to help build its next-generation Physical AI SoC. You will partner with architects, performance modelers, software, verification and physical design teams to translate innovative concepts into production silicon.

You will own substantial RTL blocks, drive microarchitectural decisions, and optimize for high performance and power efficiency while supporting AI workloads and memory systems across the SoC.