Senior SoC Physical Design Engineer: Power & Signoff

Qualcomm; San Diego (CA); On-site; USD 131,000 - 173,000; Full time

Job summary

Qualcomm Technologies, Inc. is seeking a professional to independently plan and execute physical design flows for high-speed DDR, graphics, and SOC blocks with a focus on power efficiency and performance.

The role covers Floor Planning, Clock Tree Synthesis, Place and Route, PDN, timing analysis, and verification checks (LVS/DRC). You will support tapeout signoff and participate in design reviews and cross-functional meetings.

Qualifications

• Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.

Responsibilities

• Plan and perform physical design flows (DDR, graphics, SoC) focusing on power utilization and optimization.
• Perform Floor Planning, Clock Tree Synthesis, Place and Route, PDN, Timing analysis and closure.
• Conduct LVS, DRC, DFMr, and yield checks at chip and block levels.
• Support signoff closure for tapeout and participate in design reviews and project meetings.

Skills

Power optimization

SoC design experience

Education

Master's degree in Electrical Engineering

Tools

Floor Planning

Clock Tree Synthesis

Place and Route

PDN

Timing analysis

Job description

Qualcomm Technologies, Inc. is seeking a professional to independently plan and execute physical design flows for high-speed DDR, graphics, and SOC blocks with a focus on power efficiency and performance.

The role covers Floor Planning, Clock Tree Synthesis, Place and Route, PDN, timing analysis, and verification checks (LVS/DRC). You will support tapeout signoff and participate in design reviews and cross-functional meetings.