Senior Physical Design Engineer – SoC & Low-Power

Qualcomm; Santa Clara (CA); On-site; USD 190,000 - 285,000; Full time

Job summary

Qualcomm Technologies, Inc. is seeking experienced Physical Design Engineers to contribute to cutting-edge SoC and ASIC projects across AI, mobile, automotive, data center and more.

You will participate in floorplanning, CTS, low-power techniques, timing analysis, and automated design flows, collaborating with architecture and verification teams. The role emphasizes developing innovative PD methodologies, scripting tools, and sign-off readiness, with opportunities to work on multiple nodes and

Qualifications

• Bachelor�s or Master�s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
• 6+ years of ASIC design/verification experience or related work.
• Experience with Cadence Innovus and Synopsys Fusion Compiler is preferred.
• Strong scripting skills in Python, Perl, TCL, Shell.

Responsibilities

• Lead physical design flow from netlist to tape-out.
• Develop solutions for high-speed, low-power ASICs/SoCs.
• Perform floorplanning, CTS, routing, timing closure across MMMC scenarios.
• Analyze timing, signal integrity, and PD rule violations; drive ECOs.

Skills

Physical Design

Floorplanning

CTS

Timing Analysis

Scripting (Python/TCL)

Education

BS in Electrical/Computer Engineering

MS in Electrical/Computer Engineering

PhD in relevant field

Tools

Cadence Innovus

Synopsys Fusion Compiler

PrimeTime SI

Job description

Qualcomm Technologies, Inc. is seeking experienced Physical Design Engineers to contribute to cutting-edge SoC and ASIC projects across AI, mobile, automotive, data center and more.

You will participate in floorplanning, CTS, low-power techniques, timing analysis, and automated design flows, collaborating with architecture and verification teams. The role emphasizes developing innovative PD methodologies, scripting tools, and sign-off readiness, with opportunities to work on multiple nodes and