Senior ASIC Physical Design Engineer - MMMC & Low-Power

Qualcomm; San Diego (CA); On-site; USD 116,000 - 173,000; Full time

Job summary

Qualcomm Technologies, Inc. in San Diego, CA, seeks a skilled Physical Design engineer to drive all stages of the ASIC/SoC design flow from netlist to tape-out. You will develop physical design solutions for high-speed, low-power ICs and collaborate with multiple teams to ensure successful sign-off.

The role requires 2–10+ years in Physical Design, experience with Cadence Innovus and Synopsys tools, and a strong background in timing, SI, and RTL/DFT collaboration.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
• 2-10+ years of industry experience or relevant academic/project experience in Physical Design.
• Experience with Cadence Innovus and/or Synopsys Fusion Compiler.
• Experience with Static Timing Analysis and timing closure using Synopsys PrimeTime SI.
• DFT-aware physical implementation and constraint management.

Responsibilities

• Execute and drive all stages of the physical design flow from synthesized netlist to tape-out.
• Develop and implement physical design solutions for complex, high-speed, and low-power ASICs and SoCs.
• Perform floorplanning, partitioning, power planning, and IR-drop analysis.
• Execute placement, clock tree synthesis (CTS), routing, timing optimization, and timing closure across MMMC scenarios.
• Analyze and resolve timing violations, signal integrity issues, crosstalk effects, and physical design rule violations.
• Perform RC extraction, physical verification, and formal verification activities.
• Implement ECOs and support design convergence through sign-off.
• Collaborate with architecture, RTL, DFT, verification, and methodology teams to ensure project success.
• Contribute to low-power implementation methodologies and customized place-and-route solutions.
• Develop automation and productivity tools using scripting languages and software development techniques.

Skills

Strong problem solving

ASIC development/debugging

Education

Bachelor's or Master's degree in Electrical/Computer Engineering/Computer Science

Tools

Cadence Innovus

Synopsys Fusion Compiler

Synopsys PrimeTime SI

Job description

Qualcomm Technologies, Inc. in San Diego, CA, seeks a skilled Physical Design engineer to drive all stages of the ASIC/SoC design flow from netlist to tape-out. You will develop physical design solutions for high-speed, low-power ICs and collaborate with multiple teams to ensure successful sign-off.

The role requires 2–10+ years in Physical Design, experience with Cadence Innovus and Synopsys tools, and a strong background in timing, SI, and RTL/DFT collaboration.