Senior Physical Design Engineer - SoC/ASIC & Low-Power

QUALCOMM, Inc.; San Diego (CA); On-site; USD 174,000 - 262,000; Full time

Benefits offered by this job

Discretionary bonus

RSU grants

Job summary

Qualcomm Technologies, Inc. is seeking talented Physical Design Engineers to join our SoC and ASIC Design organization in San Diego. You will contribute across high-performance computing, AI, mobile, automotive, data center, and semiconductor technologies.

The role covers floorplanning, CTS, low-power implementation, timing analysis, DFT-aware flows, and automation. You will collaborate with architecture, RTL, verification, and methodology teams to enable tape-out and sign-off on MMMC paths.

Qualifications

• Bachelor's or MSc in Electrical/Computer Engineering or related field.
• 10+ years in Physical Design or equivalent experience.
• Experience with MMMC sign-off flows and advanced node design.

Responsibilities

• Execute full physical design flow from netlist to tape-out.
• Perform floorplanning, CTS, routing, timing closure.
• Analyze timing, SI, crosstalk; resolve violations.
• Develop automation and scripts; support ECOs.
• Collaborate with architecture, RTL, DFT and verification teams.

Skills

Physical Design

Place and Route

Static Timing Analysis

Power Integrity

Clock Tree Synthesis

Scripting: Python

C/C++

Linux/Unix

Education

Bachelor's degree

Master's degree

PhD

Tools

Cadence Innovus

Synopsys Fusion Compiler

Synopsys PrimeTime SI

Job description

Qualcomm Technologies, Inc. is seeking talented Physical Design Engineers to join our SoC and ASIC Design organization in San Diego. You will contribute across high-performance computing, AI, mobile, automotive, data center, and semiconductor technologies.

The role covers floorplanning, CTS, low-power implementation, timing analysis, DFT-aware flows, and automation. You will collaborate with architecture, RTL, verification, and methodology teams to enable tape-out and sign-off on MMMC paths.