Senior ASIC/SoC Physical Design Engineer

QUALCOMM, Inc.; Santa Clara (CA); Hybrid; USD 190,000 - 285,000; Full time

Job summary

Qualcomm Technologies, Inc. in Santa Clara, California is seeking a Physical Design Engineer to contribute across ASIC/SoC projects, including floorplanning, CTS, and low-power strategies.

The role involves executing the full physical design flow, collaborating with cross-functional teams, and delivering sign-off-ready results on advanced process nodes. Strong scripting and automation experience are a plus.

Qualifications

• Bachelor's or Master's degree in a related technical field with strong ASIC/SoC background.
• Experience in physical design implementation, timing closure, and sign-off.
• Proficiency with automation and scripting for design flows.

Responsibilities

• Execute and drive all stages of the physical design flow from synthesized netlist to tape-out.
• Develop and implement physical design solutions for complex high-speed, low-power ASICs and SoCs.
• Perform floorplanning, partitioning, power planning, and IR-drop analysis.
• Execute placement, clock tree synthesis (CTS), routing, timing optimization, and timing closure across MMMC scenarios.
• Analyze and resolve timing violations, signal integrity issues, crosstalk effects, and physical design rule violations.
• Perform RC extraction, physical verification, and formal verification activities.
• Collaborate with architecture, RTL, DFT, verification, and methodology teams to ensure successful project execution.
• Develop automation and productivity tools using scripting languages and software development techniques.

Skills

Physical Design

Floorplanning

CTS

Timing Closure

DFT-aware design

Python scripting

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Tools

Cadence Innovus

Synopsys Fusion Compiler

PrimeTime SI

Job description

Qualcomm Technologies, Inc. in Santa Clara, California is seeking a Physical Design Engineer to contribute across ASIC/SoC projects, including floorplanning, CTS, and low-power strategies.

The role involves executing the full physical design flow, collaborating with cross-functional teams, and delivering sign-off-ready results on advanced process nodes. Strong scripting and automation experience are a plus.