Senior SoC Power Design Engineer (Low Power)

Qualcomm; San Diego (CA); On-site; USD 140,000 - 210,000; Full time

Job summary

Qualcomm Technologies, Inc. is seeking an ASIC engineer to define, model, design, optimize, verify, and document IP for high-performance, low-power SoCs.

The role involves collaboration with RTL, DFT, Synthesis, and Physical Design teams to implement power intent and ensure low-power targets across pre-silicon to post-silicon stages. Responsibilities include generating UPF power designs, validating power features, and working with CAD partners to improve power flows.

Qualifications

• Bachelor's degree in Science, Engineering, or related field with 4+ years ASIC experience.
• Master's degree in Science, Engineering, or related field with 3+ years ASIC experience.
• PhD in Science, Engineering, or related field with 2+ years ASIC experience.

Responsibilities

• Work with frontend RTL, DFT, Synthesis, and Physical design teams in the development of power intent design at SoC level.
• Generate and validate power intent design (UPF) at SoC level.
• Review designs and guide IP designers' power intent design ensuring it meets SoC level low power implementation requirements.
• Work with design verification in validating low power design feats at SoC and IP level.
• Collaborate with company CAD and vendor to enhance existing power flows and tools.
• Improve power design flows in areas of power modeling, clock power analysis, structural power validation, IP power intent QA.
• Execute power-aware implementation flow, including UPF/CPF/Conformal Low Power Check.
• Review IP design's power features and power budgets/estimates.
• Track IP power development through the design cycle ensuring it meets power budgets - leakage/dynamic at every milestone.
• Perform power analysis/projection of SoC baseline power and deliver SoC power models to chipset.
• Execute power simulation/analysis -- (PtPx/PowerArtist/Prime Power/PowerPro)

Skills

ASIC frontend

Logic design

RTL coding

Verification

Synthesis

Timing closure

Verilog/VHDL/SystemVerilog

Power-aware flow

Scripting (Perl/Python/Tcl)

Education

Bachelor's in Electrical or Computer Engineering

Master's in Electrical or Computer Engineering

PhD in Science/Engineering

Tools

UPF/CPF/Conformal Low Power

Conformal Power/Analysis

Job description

Qualcomm Technologies, Inc. is seeking an ASIC engineer to define, model, design, optimize, verify, and document IP for high-performance, low-power SoCs.

The role involves collaboration with RTL, DFT, Synthesis, and Physical Design teams to implement power intent and ensure low-power targets across pre-silicon to post-silicon stages. Responsibilities include generating UPF power designs, validating power features, and working with CAD partners to improve power flows.