ASIC Physical Design Engineer: MMMC, Low-Power, RSU/Bonus

QUALCOMM, Inc.; San Diego (CA); Hybrid; USD 120,000 - 180,000; Full time

Job summary

Qualcomm seeks a Physical Design engineer in San Diego to lead multiple levels of ASIC/SoC implementation from synthesis to tape-out. The role covers floorplanning, CTS, placement, routing, timing closure, and sign-off across MMMC scenarios.

You will work with architecture, RTL, DFT, verification, and methodology teams to deliver low-power, high-performance designs, while developing automation and tooling in Python, Perl, TCL, and C/C++.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
• 2–10+ years of Physical Design experience or relevant academic/project work.
• Experience in ASIC/SoC Physical Design implementation and P&R flows.
• Proficiency with timing, power, and sign-off methodologies.

Responsibilities

• Execute and drive all stages of the physical design flow from synthesis to tape-out.
• Perform floorplanning, partitioning, power planning, CTS, routing, and timing closure.
• Analyze timing, SI, crosstalk, and DRC/EC violations across MMMC scenarios.
• Develop automation tools and collaborate with architecture, RTL, DFT, and verification teams.

Skills

Python

Perl

TCL

Shell scripting

C/C++

Linux/Unix

Education

Bachelor's or Master's in Electrical Engineering

Tools

Cadence Innovus

Synopsys Fusion Compiler

Synopsys PrimeTime SI

Job description

Qualcomm seeks a Physical Design engineer in San Diego to lead multiple levels of ASIC/SoC implementation from synthesis to tape-out. The role covers floorplanning, CTS, placement, routing, timing closure, and sign-off across MMMC scenarios.

You will work with architecture, RTL, DFT, verification, and methodology teams to deliver low-power, high-performance designs, while developing automation and tooling in Python, Perl, TCL, and C/C++.