Physical Design Engineer: SoC/ASIC, Low Power & Timing

Nutanix; San Diego (CA); On-site; USD 116,000 - 173,000; Full time

Benefits offered by this job

Competitive benefits

Job summary

Qualcomm Technologies, Inc. seeks talented Physical Design Engineers to join our SoC and ASIC design organization in a fast-paced environment.

You will contribute across projects spanning high-performance computing, AI, mobile, automotive, data center, and next-generation semiconductor technologies. You will execute and optimize all stages of the physical design flow, collaborate with multiple teams, and contribute to low-power implementations and automation.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
• 2-10+ years of industry experience or relevant academic/project experience in Physical Design.

Responsibilities

• Execute and drive all stages of the physical design flow from synthesized netlist to tape-out.
• Develop and implement physical design solutions for complex, high-speed, and low-power ASICs and SoCs.
• Perform floorplanning, partitioning, power planning, and IR-drop analysis.
• Execute placement, clock tree synthesis (CTS), routing, timing optimization, and timing closure across MMMC scenarios.
• Analyze and resolve timing violations, signal integrity issues, crosstalk effects, and physical design rule violations.
• Perform RC extraction, physical verification, and formal verification activities.
• Implement engineering change orders (ECOs) and support design convergence through sign-off.
• Collaborate with architecture, RTL, DFT, verification, and methodology teams to ensure successful project execution.
• Contribute to the development of innovative low-power implementation methodologies and customized place-and-route solutions.
• Develop automation and productivity tools using scripting languages and software development techniques.

Skills

Cadence Innovus

Synopsys Fusion Compiler

PrimeTime SI

Python scripting

Digital ASIC design

RTL to GDSII flow

Education

Bachelor's or Master's in Electrical/Computer Engineering or related field

PhD in Science/Engineering

Tools

Cadence Innovus

Synopsys Fusion Compiler

Synopsys PrimeTime SI

Scripting: Python/TCL

Job description

Qualcomm Technologies, Inc. seeks talented Physical Design Engineers to join our SoC and ASIC design organization in a fast-paced environment.

You will contribute across projects spanning high-performance computing, AI, mobile, automotive, data center, and next-generation semiconductor technologies. You will execute and optimize all stages of the physical design flow, collaborate with multiple teams, and contribute to low-power implementations and automation.