Staff SOC Physical Design Engineer

Qualcomm; Austin (TX); On-site; USD 152,000 - 210,000; Full time

Job summary

Qualcomm Technologies, Inc. seeks a senior hardware engineer to lead complex physical design flows for high-speed DDR and graphics in SOCs, with a focus on power optimization. You will plan floorplanning, clock tree synthesis, placement, routing, and PDN analyses to ensure signoff readiness.

The role requires a Master's degree and 3 years of related experience, with collaboration across cross-functional teams and participation in design reviews for tapeout readiness.

Qualifications

• Master's degree in a relevant field and three (3) years of experience in a related occupation.

Responsibilities

• Lead, plan and synthesize ambiguous or conflicting requirements for complex physical design flows.
• Oversee physical design flow for high-speed DDR, graphics, and SoC algorithms and modeling, focusing on power optimization.
• Perform Floor Planning, Clock Tree Synthesis, Place and Route, PDN, timing analysis and closure.
• Conduct LVS, DRC, design-for-manufacturing and design-for-yield checks at chip and block levels.
• Support cross-functional teams to drive signoff closure for tapeout and participate in design reviews.

Education

Master's degree in Electrical Engineering, Computer Engineering, Computer Science or related degree field

Job description

Company

Qualcomm Technologies, Inc.

Job Area

Engineering Group, Engineering Group > ASICS Engineering

General Summary

This individual leads, plans, synthesizes ambiguous or conflicting requirements and performs the complex responsibility of the Physical Design Flow of high-speed DDR, graphics, physical verification flows, micro-architecture, SOC algorithm design and modeling, and methodology, focusing on target power utilization and optimization for system-on-chip (SoC) products and how these features impact power and performance. Responsibilities include: Floor Planning, Clock Tree Synthesis, Place and Route, PDN, Timing analysis and closure. Performs various physical verification checks (such as LVS, DRC, design-for-manufacturing & design-for-yield) at the chip and block levels. Provides schedules and support cross-functional engineering effort to drive to signoff closure for tapeout. Acts as a strong contributor at design reviews and project meetings and communicates and implements a development plan.

Will accept a Master's Degree (or foreign academic equivalent) in Electrical Engineering, Computer Engineering, Computer Science or related degree field and three (3) years of experience in a related occupation

Pay Range: $152,360.00 - $210,000.00/year

Applicants:

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