Senior SoC PD Engineer – Lead Tapeout & PPA

Xcelerium; Irvine (CA); Sur place; USD 130 000 - 180 000; Plein temps

Avantages offerts par ce poste

Competitive compensation package

Résumé du poste

A semiconductor company is seeking a Senior SoC/ASIC Physical Design Engineer who will lead the physical design activities and collaborate closely with engineering teams. This role involves establishing modern design flows and optimizing performance while focusing on design closure, employing cutting-edge technologies in developing edge processors. Candidates with over 10 years of experience in ASIC/SoC design and strong expertise in Synopsys EDA tools are preferred. An excellent compensation package is offered.

Qualifications

• 10+ years of experience in ASIC/SoC physical design and flow development.
• Proficient in physical design methodologies: synthesis, place & route, STA, formal verification.
• Skilled in extraction and analysis of design parameters and implementing voltage scaling.

Responsabilités

• Establish a modern physical design flow utilizing EDA tool fusion.
• Perform partition synthesis and physical implementation tasks.
• Create and refine physical design methodologies and automation scripts.
• Work closely with RTL, DFT, and ASIC design teams.
• Utilize an objective, metrics-driven approach to ensure design closure.
• Lead signoff closure activities including static timing analysis.

Connaissances

Expertise in RTL-to-GDSII physical design and signoff flows

Strong experience with Synopsys EDA tools

Proficient in physical design methodologies

Knowledge of FinFET and deep sub-micron CMOS technologies

Proficient in scripting languages (Python, Tcl, Perl, bash/csh)

Formation

Bachelor’s degree in Electrical Engineering

Master’s degree preferred

Outils

Synopsys EDA tools

Description du poste

A semiconductor company is seeking a Senior SoC/ASIC Physical Design Engineer who will lead the physical design activities and collaborate closely with engineering teams. This role involves establishing modern design flows and optimizing performance while focusing on design closure, employing cutting-edge technologies in developing edge processors. Candidates with over 10 years of experience in ASIC/SoC design and strong expertise in Synopsys EDA tools are preferred. An excellent compensation package is offered.