Senior SoC/ASIC Physical Design Engineer

Sigmaways Inc; Irvine (CA); Sur place; USD 150 000 - 190 000; Plein temps

Résumé du poste

A leading semiconductor design firm is seeking a Senior SoC/ASIC Physical Design Engineer in Irvine, California. The role involves driving physical design activities to closure while collaborating with RTL and engineering teams. Requirements include a Bachelor’s degree (Master’s preferred) and at least 10 years of experience in ASIC/SoC physical design with expertise in EDA tools. You will focus on optimizing performance, power, and area while leading design closure activities. Competitive salary and benefits offered.

Qualifications

• At least 10 years of experience in ASIC/SoC physical design and flow development.
• Expertise in RTL-to-GDSII design flows including synthesis and place & route.
• Proficient in automation scripting with Python, Tcl, Perl, and bash/csh.

Responsabilités

• Build modern physical design flows using EDA tools and machine learning.
• Perform synthesis, floorplanning, and PDN generation.
• Lead closure activities including STA, noise analysis, and physical verification.

Connaissances

ASIC/SoC physical design

EDA tool fusion

Python scripting

Power optimization techniques

Collaboration skills

Formation

Bachelor’s in Electrical Engineering, Computer Engineering, or Computer Science

Master’s preferred

Outils

Synopsys EDA tools

Description du poste

We are seeking a Senior SoC/ASIC Physical Design Engineer to drive physical design activities to successful closure by collaborating closely with RTL and cross-functional engineering teams.

In this role, you will develop, refine, and implement cutting-edge flows and methodologies that optimize performance, power, and area (PPA), directly contributing to world class time to closure and tapeout with optimal team efficiency and resource allocation.

Responsibilities:

• Build modern physical design flows using EDA tool fusion and machine learning to optimize PPA, resources, and accelerate time-to-closure.
• Perform synthesis, floorplanning, PDN generation, place & route, timing, noise, verification, EM/IR checks, and signoff.
• Create and refine PD methodologies and automation scripts to streamline design and signoff processes.
• Partner with RTL, DFT, and ASIC teams to define architectural feasibility, timing/power/area targets, and design trade-offs.
• Apply a metrics-driven approach to resolve design and timing challenges and ensure predictable milestone delivery.
• Lead closure activities, including STA, noise analysis, logic equivalency, physical verification, and power integrity (EM/IR).

Qualifications:

• Bachelor’s in Electrical Engineering, Computer Engineering, or Computer Science .Master’s preferred
• At least 10 years of experience in ASIC/SoC physical design and flow development.
• Expertise in RTL-to-GDSII design flows, Synopsys EDA tools, and advanced PD methodologies like synthesis, place & route, STA, CDC, power analysis.
• Knowledge of FinFET/deep sub-micron CMOS, DFT methodologies like Scan, MBIST, LBIST and power/IR drop management.
• Strong ability to analyze design parameters and QoR metrics and implement advanced power optimization techniques such as SVS, DVFS, and SRAM split-rail architectures.
• Proficient in Python, Tcl, Perl, bash/csh, and automation scripting.
• Strong analytical and problem solving skills with proven ability to lead design closure and collaborate across teams.