SoC Implementation Leader — End-to-End PD & Tapeout

NXP Semiconductors; Austin (TX); On-site; USD 180,000 - 260,000; Full time

Job summary

NXP Semiconductors in Austin, TX is seeking a highly experienced leader to head SoC Implementation / Physical Design for advanced semiconductor products. This role owns end-to-end physical design from RTL to silicon and leads global teams to deliver high-quality silicon on aggressive schedules.

The ideal candidate has 17+ years in ASIC/SoC physical design, strong leadership, and deep expertise in EDA tools (Synopsys/Cadence).

Qualifications

• Bachelor’s or Master’s in Electrical / Electronics Engineering or related field.
• 17+ years of experience in ASIC / SoC physical design
• Proven experience leading large-scale SoC programs
• Strong knowledge of industry EDA tools (Synopsys, Cadence flows)
• Demonstrated success in advanced node implementations
• Strong leadership, communication, and stakeholder management skills

Responsibilities

• End-to-End Physical Design Ownership: Lead complete SoC physical design execution from RTL to tapeout.
• Drive timing, power, IR/EM, and physical verification closure to tapeout readiness.
• Deliver optimized PPA across complex designs.
• Align with internal expectations of implementing designs on silicon with optimal quality, cost efficiency.

Skills

SoC leadership

RTL-to-GDSII flow

Program management

Stakeholder management

Education

Electrical/Electronics Engineering

Tools

Synopsys

Cadence

Job description

NXP Semiconductors in Austin, TX is seeking a highly experienced leader to head SoC Implementation / Physical Design for advanced semiconductor products. This role owns end-to-end physical design from RTL to silicon and leads global teams to deliver high-quality silicon on aggressive schedules.

The ideal candidate has 17+ years in ASIC/SoC physical design, strong leadership, and deep expertise in EDA tools (Synopsys/Cadence).