Physical Design Lead

Alexander Chapman Ltd; San Francisco (CA); On-site; USD 180,000 - 260,000; Full time

Job summary

Alexander Chapman Ltd in San Francisco seeks an experienced Implementation Lead to drive end-to-end physical design of advanced silicon and AI hardware. You will own floorplanning, CTS, routing, and timing closure for high-performance ASICs/SoCs, while pushing AI-driven optimization and automation across large-scale designs.

The role requires 5+ years in physical design, strong scripting (Python/Tcl), and expertise with EDA toolchains.

Qualifications

• 5+ years hands-on physical design experience.
• Ownership of complex ASIC or SoC implementations through tape-out.
• Strong Python and Tcl scripting for PD automation.
• Experience with advanced-node implementation and EDA tools.
• Exposure to AI/ML-driven EDA optimization and design-space exploration.

Responsibilities

• Lead physical implementation of complex ASICs and compute subsystems from floorplanning through tape-out.
• Own placement, clock tree synthesis, routing, timing closure, and physical sign-off.
• Develop and optimize implementation methodologies for large-scale designs.
• Integrate machine learning and automated optimization into PD workflows to improve PPA and efficiency.
• Address power integrity, thermal, congestion, and timing challenges.
• Develop scalable automation frameworks to accelerate design iterations and improve quality.

Skills

Physical design

ASIC / SoC

Floorplanning

Placement

Clock tree synthesis

Routing

Timing closure

EDA tools

Python scripting

Tcl scripting

AI/ML optimization

Automation frameworks

Power integrity

Thermal analysis

Tools

Synopsys Suite

Cadence Innovus

Mentor Graphics

Job description

Implementation Lead - Advanced Silicon & AI Hardware

Role Overview

Seeking an experienced Physical Design Lead to drive end-to-end implementation of advanced compute architectures, with a focus on performance, power, area (PPA), and design automation. The role combines hands-on silicon implementation, technical leadership, and AI-driven optimization across complex SoC designs.

Key Responsibilities

• Lead physical implementation of complex ASICs and high-performance compute subsystems from floorplanning through tape-out.
• Own placement, clock tree synthesis, routing, timing closure, and physical sign-off across advanced process nodes.
• Develop and optimize implementation methodologies for large-scale designs, including memory-intensive architectures and high-bandwidth interfaces.
• Integrate machine learning and automated optimization techniques into physical design workflows to improve PPA and execution efficiency.
• Address complex power integrity, thermal, congestion, and timing challenges.
• Develop scalable automation frameworks to accelerate design iterations and improve implementation quality.

Requirements

• 5+ years of hands-on physical design experience, including ownership of complex ASIC or SoC implementations through tape-out.
• Strong expertise in floorplanning, placement, CTS, routing, timing closure, and sign-off.
• Experience with advanced-node implementation and industry-standard EDA tools.
• Exposure to AI/ML-driven EDA optimization, automated design-space exploration, or reinforcement learning techniques.
• Deep understanding of STA, DRC, LVS, EM/IR, and PPA optimization.
• Strong Python and Tcl scripting skills for physical design automation and custom workflows.
• Ability to independently drive technical decisions and lead complex implementation initiatives.