Senior Physical Design Engineer (Remote) - PPA/Tapeout

Chelsea Search Group; Orlando (FL); Remote; USD 140,000 - 180,000; Full time

Job summary

Chelsea Search Group is seeking a Senior/Principal Physical Design Engineer to own physical implementation of complex ASICs, from RTL to GDSII. You will drive floorplanning, CTS, routing, timing closure, and PPA optimization using industry-standard tools in a highly collaborative environment.

The role requires 10+ years in ASIC/SoC, strong Verilog/SystemVerilog expertise, and a track record of first-pass success.

Qualifications

• 10+ years of direct ASIC/SoC experience.
• Proficient in RTL-based digital IC design using Verilog/SystemVerilog.
• Strong understanding of digital design principles and PPA tradeoffs.
• Experience with industry-standard EDA tools and methodologies.
• Willingness to mentor and lead other engineers.

Responsibilities

• Analyze and optimize designs to meet PPA, timing, SI, reliability, and manufacturability requirements.
• Collaborate with RTL, verification, DFT, analog/mixed-signal, and packaging teams for chip integration.
• Develop and optimize floorplans with high-speed interfaces like DDR/SerDes.
• Maintain and improve physical design flows, scripts, and automation to improve efficiency.
• Perform full-chip design implementation from RTL to GDSII, including CTS and routing.
• Conduct timing closure across multiple modes and corners; address physical verification issues.

Skills

ASIC/SoC design

Verilog/SystemVerilog

PPA optimization

Floorplanning/CTS/Routing

Leadership/mentoring

Problem solving

Education

BSEE / MS in EE or equivalent

Tools

Synopsys Fusion Compiler

Siemens Calibre

EDA toolchain

Job description

Chelsea Search Group is seeking a Senior/Principal Physical Design Engineer to own physical implementation of complex ASICs, from RTL to GDSII. You will drive floorplanning, CTS, routing, timing closure, and PPA optimization using industry-standard tools in a highly collaborative environment.

The role requires 10+ years in ASIC/SoC, strong Verilog/SystemVerilog expertise, and a track record of first-pass success.