Senior Physical Design Engineer: Tapeouts & Equity

Bolt Graphics, Inc.; Sunnyvale (CA); On-site; USD 200,000 - 220,000; Full time

Benefits offered by this job

Medical, Dental, & Vision insurance premiums covered

Equity - Stock Options

401(k) match

Job summary

A semiconductor startup based in California is seeking a Staff/Senior Staff Physical Design Engineer to drive full-chip implementations and meet PPA targets. This role requires 8–12 years of experience in ASIC physical design, specializing in tools like Synopsys ICC2 and Cadence Innovus. The ideal candidate will have a strong background in full-chip or large block implementations and a hands-on approach to debugging. The compensation range is competitive, between $200,000 and $220,000 per year.

Qualifications

• 8–12 years of experience in ASIC physical design.
• Proven experience in full-chip or large block implementation and tapeouts.
• Strong expertise in power planning and physical verification.

Responsibilities

• Drive full-chip or block-level physical implementation from netlist to GDSII.
• Achieve timing, power, and area (PPA) targets.
• Collaborate with RTL, architecture, and verification teams.

Skills

Full-chip implementation

Static Timing Analysis (STA)

Placement

Debugging skills

Scripting in TCL/Python

Education

Bachelor’s/Master’s in Electrical Engineering or related field

Tools

Synopsys ICC2

Cadence Innovus

Job description

A semiconductor startup based in California is seeking a Staff/Senior Staff Physical Design Engineer to drive full-chip implementations and meet PPA targets. This role requires 8–12 years of experience in ASIC physical design, specializing in tools like Synopsys ICC2 and Cadence Innovus. The ideal candidate will have a strong background in full-chip or large block implementations and a hands-on approach to debugging. The compensation range is competitive, between $200,000 and $220,000 per year.