DFT Engineer - SoC/ASIC ATPG & MBIST

Prime Hiring Solutions; San Jose (CA); On-site; USD 140,000 - 190,000; Full time

Job summary

Prime Hiring Solutions is seeking a DFT/ATPG engineer for SoC/ASIC environments in California. The role demands hands-on experience in DFT and ATPG, MBIST architectures, IO test methodologies, and strong RTL fundamentals.

You will work with industry-standard DFT/ATPG tools in a fast-paced semiconductor program, applying analytical and problem-solving skills daily. The ideal candidate has 4+ years of relevant experience, excellent communication abilities, and a solid grasp of clock DFT and

Qualifications

• 4+ years of hands-on experience in DFT and ATPG for SoC or ASIC designs.
• Strong understanding of DFT fundamentals including controllability, observability, and scan-based testing.
• Proven expertise in ATPG pattern generation, analysis, and debug.
• Experience with MBIST, including memory test architectures and diagnostics.
• Knowledge of IO Test methodologies for interface and pin level validation.
• Solid understanding of clock DFT and clock verification concepts.
• Strong grasp of digital design and RTL fundamentals.
• Experience with industry standard DFT/ATPG EDA tools.
• Ability to work effectively in fast paced, high performance semiconductor programs.
• Strong analytical, problem solving, and communication skills.

Skills

DFT/ATPG experience

DFT fundamentals

ATPG pattern gen

MBIST

IO test methods

Clock DFT

RTL fundamentals

DFT/ATPG tools

Fast-paced work

Analytical skills

Tools

EDA tools

Job description

Prime Hiring Solutions is seeking a DFT/ATPG engineer for SoC/ASIC environments in California. The role demands hands-on experience in DFT and ATPG, MBIST architectures, IO test methodologies, and strong RTL fundamentals.

You will work with industry-standard DFT/ATPG tools in a fast-paced semiconductor program, applying analytical and problem-solving skills daily. The ideal candidate has 4+ years of relevant experience, excellent communication abilities, and a solid grasp of clock DFT and