Lead ASIC DFT Engineer — ATPG, BIST & Test Flow

Broadcom, Inc.; Irvine (CA); On-site; USD 129,000 - 207,000; Full time

Benefits offered by this job

Annual bonus

Equity grants

401(k) matching

ESP P

Health, dental and vision plans

Paid holidays and vacation

Job summary

Broadcom's ASIC Product Division is seeking a DFT Engineer for ASIC/Chip level ATPG to lead DFT programs from specification through production release. You will collaborate with physical design, STA, and external customers to drive DFT architecture, test insertion, pattern generation, and yield improvement across 3nm and beyond.

The role involves extensive scripting automation (Python/TCL/C++), ATPG verification, and silicon bring-up with ATE testing to meet stringent test metrics.

Qualifications

• Strong DFT architecture and implementation background (Scan, BIST, IO/Analog DFT, IJTAG/IEEE 1687, IEEE 1149.1/1149.6)
• Experience with memory and logic BIST strategies, verification, and debug across embedded memories (SRAM, CAM, RF, ROM)
• Hands-on Verilog coding, testbench development, ATPG pattern generation, simulation, and timing constraints/Test-STA

Responsibilities

• Understand Broadcom and customer DFT feature requirements and DPPM goals to define appropriate DFT specifications for the ASIC
• Implement DFT architectures, including Scan, MBIST, TAP, LBIST, IO, SerDes, and IP DFT integration
• Perform ATPG and verification at the ASIC/chip level, as well as rapid bring-up of ATE test patterns
• Collaborate with STA and design integration engineers for timing and design closure
• Generate, verify, and debug test vectors prior to tapeout release
• Validate and debug test vectors on ATE during silicon bring-up
• Assist with silicon failure analysis, diagnostics, and yield improvement efforts
• Interface with customers, physical design teams, and global test engineering/manufacturing teams
• Work with IP DFT engineers and cross-functional stakeholders
• Debug customer-returned parts (RMA) on ATE
• Develop DFT solutions for advanced process nodes (3nm+) and automate DFT/test vector flows

Skills

DFT architecture

ATPG pattern generation

Verilog coding

Testbench development

Debug and yield analysis

Python/TCL/C++ scripting

Cross-functional collaboration

Education

Bachelor's in Electrical/Electronic/Computer Engineering

12+ years of experience or Master’s with 10+ years

Tools

DFT Compiler

TestKompress

TetraMax

FastScan

Job description

Broadcom's ASIC Product Division is seeking a DFT Engineer for ASIC/Chip level ATPG to lead DFT programs from specification through production release. You will collaborate with physical design, STA, and external customers to drive DFT architecture, test insertion, pattern generation, and yield improvement across 3nm and beyond.

The role involves extensive scripting automation (Python/TCL/C++), ATPG verification, and silicon bring-up with ATE testing to meet stringent test metrics.