ASIC Packaging SI/PI Engineer - Hybrid (San Jose)

Cisco; San Jose (CA); On-site; USD 150,000 - 230,000; Full time

Benefits offered by this job

Medical, dental and vision insurance

401(k) with Cisco matching

Paid parental leave

Flexible vacation policy

Job summary

Cisco Silicon One is seeking a Signal and Power Integrity Engineer to develop next-generation ASIC packaging and verify SI/PI across interposer, substrate, and PCB. You will define design rules and collaborate with layouts and system partners to meet power, performance, and area targets.

The role requires strong background in high-speed signaling, SI/PI simulations, and post-layout extraction. You will work on high-volume packaging and contribute to cross-disciplinary efforts in a fast-paced

Qualifications

• Bachelor's/Master's/PhD in EE with related SI/PI experience.
• Experience with high-speed design principles and 56G PAM4 SerDes architectures.
• Experience with pre- and post-layout SI/PI simulations with Cadence Sigrity, Ansys HFSS, and Keysight ADS.
• Layout reviews and physical validation using Cadence APD and Ansys EM flows.
• Circuit-level analysis using SPICE.

Responsibilities

• Develop, document, and implement design rules for ultra-high-speed signaling, ensuring power, performance, and area goals are met for products.
• Analyze substrate signal integrity (SI) and power integrity (PI) and advise layout team.
• Design, document, and develop ASIC packages for high-volume, high-quality release, including post-layout extraction and reporting.
• Collaborate with system partners, vendors, and design leads to resolve complex technical issues using advanced technology design rules.

Skills

High-Speed Design

SI/PI Simulation

Layout Review

Circuit Analysis

Education

Bachelor's degree in Electrical Engineering

Master's degree in Electrical Engineering

PhD in Electrical Engineering

Tools

Cadence Sigrity

Ansys HFSS

Keysight ADS

Cadence APD

Job description

Cisco Silicon One is seeking a Signal and Power Integrity Engineer to develop next-generation ASIC packaging and verify SI/PI across interposer, substrate, and PCB. You will define design rules and collaborate with layouts and system partners to meet power, performance, and area targets.

The role requires strong background in high-speed signaling, SI/PI simulations, and post-layout extraction. You will work on high-volume packaging and contribute to cross-disciplinary efforts in a fast-paced