Silicon Packaging Engineer (SIPI)

Meta; Menlo Park (CA); On-site; USD 178,000 - 250,000; Full time

Job summary

Meta seeks an experienced Signal Integrity and Power Integrity (SI/PI) Engineer to own chip-package-system co-design for AI accelerators and HPC silicon. You will drive SI/PI requirements from architecture through post-silicon validation across 2.5D/3D packages with ASIC, package, PCB, and OSAT partners.

Responsibilities include leading DPCO, substrate/interposer decisions, and validation of high-speed interfaces (HBM, PCIe, SerDes).

Qualifications

• 8+ years of SI/PI analysis, simulation, and measurement.
• Proficient with HFSS, Sigrity, Hspice or similar tools.
• Impedance control and PDN characterization knowledge.
• Experience with 2.5D/3D packaging concepts.
• Expertise in high-speed interconnects (HBM, D2D, PCIe, Ethernet).
• Familiarity with memory, SIPI models and timing budgets.
• Package-level SI/PI across silicon, package, and board.

Responsibilities

• Lead chip-package-system co-design for HPC and AI silicon.
• Drive SI/PI requirements from architecture to post-silicon validation.
• Own substrate/interposer stack-up and material selection.
• Define high-speed interface channels and PDN analysis.
• Develop SI/PI methodology and validate with tests.

Skills

SI/PI experience

HFSS

Sigrity

Hspice

2.5D/3D packaging

HBM

PCIe/SerDes

Power integrity

Tools

Cadence Sigrity

PowerSI

Ansys SIwave

Keysight ADS

Ansys HFSS

Job description

Job Overview

We are seeking a highly skilled Signal Integrity and Power Integrity (SI/PI) Engineer to own chip-package-system co-design for next-generation AI accelerator and high-performance computing silicon. In this role you will drive SI/PI requirements from architecture definition through post-silicon validation across 2.5D/3D heterogeneous packages — silicon interposer, RDL fan-out, wafer-on-wafer die stacking, and high-density organic substrates. You will work closely with ASIC architecture, physical design, package layout, PCB, and foundry/OSAT partners to ensure high-speed interfaces and power delivery networks meet performance, margin, and reliability targets before tape-out and Gerber release.

Silicon Packaging Engineer Responsibilities

• Chip-Package-System Co-Design: Drive SI/PI requirements analysis and optimization into product definition — chip floorplan, bump map, power tree structure, and net topology — for HPC and AI silicon built on 2.5D/3D package technology.
• Die-Package-Board Co-Optimization (DPCO): Partner with package layout and physical design to converge bump assignment, escape routing, and stack-up decisions across multiple disparate chiplets.
• Package SI/PI Ownership: Lead ASIC package SI/PI design activities including substrate and interposer stack-up and material selection, design guide authoring, layout review, and post-layout sign-off.
• High-Speed Interfaces: Own channel design and margining for HBM/HBM4/UHBM, UCIe and other die-to-die links, PCIe Gen 5/Gen 6, Ethernet SerDes, and next-generation memory interfaces.
• Power Delivery: Execute package and board PDN AC+DC analysis for low-voltage/high-current supplies, including impedance targeting, decoupling optimization, IR drop, and di/dt noise.
• Simulation Flow: Lead pre-layout and post-layout simulation flows for high-speed I/O and PDN build simulation models and develop reusable SI/PI methodology.
• Timing & Budgets: Develop and maintain interface timing budgets and voltage/noise budgets spanning silicon IO PHY, package, and board.
• Tool & Flow Development: Improve the accuracy and turnaround time of SI/PI flows through automation and correlation-driven model refinement.
• Validation Methodology: Define SI/PI validation methodology and detailed engineering test plans.
• Post-Silicon: Conduct post-silicon validation and qualification of high-speed interfaces measure PDN impedance and channel performance in the lab and correlate against simulation.
• Failure Analysis: Support Design Validation teams on SI/PI failure analysis and drive corrective design guidance back into the flow.
• Work across Architecture, ASIC, Mixed Signal, Package, PCB, and System teams to ensure package and system SI/PI performance meets expectation before Gerber out.
• Engage foundries and OSATs (e.g., TSMC CoWoS/SoIC, Intel EMIB) and memory suppliers on emerging interconnect and die-stacking standards.

Minimum Qualifications

• 8+ years of experience with signal integrity analysis, simulation, and measurement
• Proficient with HFSS, Sigrity, Hspice, and/or other simulation tools
• Proven understanding of impedance control, transmission line and PDN characterization, feasibility study and create practical design guidelines
• Experience with 2.5D/3D package design (e.g., silicon interposer, silicon bridge, 3D die stacking, STA, Voltage budget, complex SIPI models, frequency, and time domain simulation)
• Expertise in signal and power integrity for various high speed interconnects (e.g., HBMx, D2D, Ethernet, PCIe and etc)
• Familiarity with post-Si test environment on memory (HBM/ /DDR4/LPDDR4/DDR5/LPDDR5) or high speed SERDES
• Familiarity to next generation memory and chiplet standards and timing budget methodology
• Package-level signal integrity and power integrity understanding including silicon, package, and board

Preferred Qualifications

• 10+ years of experience in SIPI simulation and validation areas
• Experience with high-speed interface protocols such as MIPI, PCIe, memory, HBMand USB
• Experience using Cadence Sigrity, PowerSI, Ansys SIwave, Keysight ADS, 3D layout and Ansys HFSS
• 8+ years of experience in SIPI fundamentals, familiar with substrate/PCB design and manufacture process
• Experience in collaborating with cross-functional teams, including chip top design, physical design, Static Timing Analysis (STA), package, and system teams
• Solid understanding and experiences in computational electromagnetics and transmission line theory

About Meta

Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today—beyond the constraints of screens, the limits of distance, and even the rules of physics.

Meta is proud to be an Equal Employment Opportunity and Affiulitive Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment.

Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at [e-mail].

Compensation & Benefits

$178,000/year to $250,000/year + bonus + equity + benefits

Individual compensation is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base hourly rate, monthly rate, or annual salary only, and do not include bonus, equity or sales incentives, if applicable. In addition to base compensation, Meta offers benefits. Learn more about benefits at Meta.