Lead SI/PI Architect — High-Speed Interconnects & Packaging

NVIDIA Corporation; Santa Clara (CA); On-site; USD 320,000 - 489,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA Corporation in Santa Clara, CA is seeking a Distinguished Signal & Power Integrity Engineer to lead advanced SI strategies for high-speed interconnects and packaging across AI and HPC platforms. The role requires 15+ years of experience and a strong record in deploying next-gen technologies.

You will shape standards for UCIe, HBM, DDR, PCIe, and SerDes, mentor teams, and guide research toward scalable, high-volume manufacturing solutions while aligning with executive priorities.

Qualifications

• 15+ years leading innovations in high-speed signaling, electromagnetics, and packaging.
• Hands-on invention and deployment of advanced solutions like EMIB, UCIe, CPO.
• Experience managing and mentoring teams from research to high-volume manufacturing.

Responsibilities

• Lead development and execution of corporate-level strategies for high-speed signaling.
• Oversee direction and implementation for next-gen products from ultra-mobile to AI/HPC.
• Architect interconnect and packaging solutions for UCIe, HBM, DDR, PCIe, SerDes.
• Enable packaging technology for co-packaged optics, chiplet architectures, IVR.
• Develop modeling and characterization flows, automation, and high-volume manufacturing techniques.
• Provide strategic counsel to senior leadership on signaling, packaging, and system integration.

Skills

High-speed signaling

Computational electromagnetics

Semiconductor packaging

Education

MS/PhD in Electrical Engineering or equivalent

Job description

NVIDIA Corporation in Santa Clara, CA is seeking a Distinguished Signal & Power Integrity Engineer to lead advanced SI strategies for high-speed interconnects and packaging across AI and HPC platforms. The role requires 15+ years of experience and a strong record in deploying next-gen technologies.

You will shape standards for UCIe, HBM, DDR, PCIe, and SerDes, mentor teams, and guide research toward scalable, high-volume manufacturing solutions while aligning with executive priorities.